WilliamMiceli 352aeefd1b Made to write only once on positive edge of clock, Vivado now recognizes it as RTL_RAM

2019-03-29 16:13:50 -04:00

..

ALU.v

Added drivers for unused operations in MUX, so Vivado doesn't show the warning of being undriven

2019-03-29 16:11:52 -04:00

BasicModules.v

Added zeroing instr

2019-03-16 14:34:36 -04:00

ControlUnit.v

Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

2019-03-24 16:06:29 -04:00

CPU9bits.v

Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

2019-03-24 19:31:28 -04:00

dataMemory.v

Made to write only once on positive edge of clock, Vivado now recognizes it as RTL_RAM

2019-03-29 16:13:50 -04:00

FetchUnit.v

Better Sim

2019-03-14 14:37:58 -04:00

instructionMemory.v

Now Asynchronous and recognized by Vivado as RTL_ROM

2019-03-29 16:13:07 -04:00

RegFile.v

Fixed bugs, finished BEQ, Added Halt

2019-03-13 11:14:52 -04:00