91 lines
1.8 KiB
Verilog
91 lines
1.8 KiB
Verilog
`timescale 1ns / 1ps
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module CPU9bits(input wire [8:0] instr,
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input wire reset, clk,
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output reg done
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);
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wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;
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wire [2:0] FU, aluOp;
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wire addiS, RegEn, loadS;
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RegFile RF(
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.clk(clk),
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.reset(reset),
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.enable(RegEn),
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.write_index(instr[4:3]),
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.op0_idx(instr[4:3]),
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.op1_idx(instr[2:1]),
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.write_data(RFIn),
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.op0(op0),
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.op1(op1)
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);
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FetchUnit FetchU(
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.clk(clk),
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.reset(reset),
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.op_idx(FU[0]),
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.AddrIn(FUAddr),
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.AddrOut(PCout)
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);
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ALU alu(
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.opcode(aluOp),
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.operand0(op0),
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.operand1(op1),
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.result(AluOut)
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);
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ControlUnit CU(
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.instIn(instr[8:5]),
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.functBit(instr[0]),
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.aluOut(aluOp),
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.FU(FU),
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.addi(addiS),
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.mem(loadS),
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.load(loadMux)
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);
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//-----------------------Fetch Unit Stuff
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add_9bit JBAdder(
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.A(PCout),
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.B(JBRes),
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.Cin(9'b000000000),
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.Sum(FUJB));
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mux_2_1 mux1(
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.A(op1),
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.B(FUJB),
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.out(FUAddr),
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.switch(FU[1]));
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mux_2_1 mux2(
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.A({4'b0000,instr[4:0]}),
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.B({6'b000000,instr[2:0]}),
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.out(JBRes),
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.switch(FU[2]));
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///--------------------------Addi Stuff
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add_9bit Addier(
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.A({6'b000000,instr[2:0]}),
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.B(op1),
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.Cin(9'b000000000),
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.Sum(AddiOut));
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mux_2_1 mux3(
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.A(AluOut),
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.B(AddiOut),
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.out(loadMux),
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.switch(addiS));
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mux_2_1 mux4(
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.A(loadMux),
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.B(dataMemOut),
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.out(RFIn),
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.switch(loadS));
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endmodule |