WilliamMiceli 81cdf3c62b Added AND gate module

2019-02-15 14:59:38 -05:00

lab2CA.cache/wt

Added 1-bit adder

2019-02-15 14:55:11 -05:00

lab2CA.ip_user_files

fetch unit

2019-02-15 11:20:14 -05:00

lab2CA.srcs/sources_1/new

Added AND gate module

2019-02-15 14:59:38 -05:00

.gitignore

Initial commit, gitignore

2019-02-08 18:10:13 -05:00

lab2CA.xpr

Modularized project; mux, clock, and reg done; Progress on RegFile

2019-02-15 12:24:26 -05:00

vivado.jou

Forgot to stage this file

2019-02-15 11:53:54 -05:00

Description

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5.2 MiB

Languages

C 33.3%

Verilog 26.9%

PureBasic 23.7%

Tcl 16.1%