Added AND gate module

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -12,6 +12,15 @@ module adder_1bit(
 
 endmodule
 
+module and_gate(
+    input wire A,
+    input wire B,
+    output wire C);
+
+    assign C = A & B;
+
+endmodule
+
 module gen_clock();
 
     reg clk;