WilliamMiceli 9db4c1253b Fixed unconnected wires/ports

2019-03-29 17:22:06 -04:00

..

ALU.v

Fixed unconnected wires

2019-03-29 17:21:29 -04:00

BasicModules.v

Fixed unconnected wires/ports

2019-03-29 17:22:06 -04:00

ControlUnit.v

Reordered case statement by opcode and improved comment labels

2019-03-29 16:17:27 -04:00

CPU9bits.v

Removed CLK, as it is not needed

2019-03-29 16:16:36 -04:00

dataMemory.v

Simplified testbench a little

2019-03-29 16:16:11 -04:00

FetchUnit.v

Better Sim

2019-03-14 14:37:58 -04:00

instructionMemory.v

Removed references to CLK, as not needed; simplified testbench a little

2019-03-29 16:15:47 -04:00

RegFile.v

Fixed bugs, finished BEQ, Added Halt

2019-03-13 11:14:52 -04:00