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f34b3d40983263a5f1cd99e17b3f74f7e2c77d0f
WMU-ECE-3570-Lab
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lab2CA.srcs
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sources_1
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History
Johannes
f34b3d4098
Update
2019-04-06 13:16:35 -04:00
..
ALU.v
Fixed unconnected wires
2019-03-29 17:21:29 -04:00
BasicModules.v
Update
2019-04-06 13:16:35 -04:00
ControlUnit.v
Fixed indentations
2019-03-29 17:28:50 -04:00
CPU9bits.v
Modified sensitivities for result; Vivado metadata
2019-03-30 15:59:43 -04:00
dataMemory.v
Added pipeline registers
2019-04-06 13:13:47 -04:00
FetchUnit.v
Better Sim
2019-03-14 14:37:58 -04:00
instructionMemory.v
Added pipeline registers
2019-04-06 13:13:47 -04:00
RegFile.v
Registers and Banks don't need an enable, should be ignored using MUXes
2019-03-29 18:10:13 -04:00