WilliamMiceli f4b2ddebc1 Added back enable signals

2019-04-06 14:17:10 -04:00

..

ALU.v

Fixed unconnected wires

2019-03-29 17:21:29 -04:00

BasicModules.v

Reverting removing the enable signals to test if that is the issue

2019-04-06 14:15:51 -04:00

ControlUnit.v

Fixed indentations

2019-03-29 17:28:50 -04:00

CPU9bits.v

Added back enable signals

2019-04-06 14:17:10 -04:00

dataMemory.v

Increased memory size to get rid of unused address ports warning

2019-03-29 17:23:00 -04:00

FetchUnit.v

Better Sim

2019-03-14 14:37:58 -04:00

instructionMemory.v

Removed references to CLK, as not needed; simplified testbench a little

2019-03-29 16:15:47 -04:00

RegFile.v

Reverting removing the enable signals to test if that is the issue

2019-04-06 14:15:51 -04:00