William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fixed bugs, finished BEQ, Added Halt

Browse Source
This commit is contained in:
jose.rodriguezlabra
2019-03-13 11:14:52 -04:00
parent 911d8e31cc
commit 026eb65861
69 changed files with 1145 additions and 1038 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
lab2CA.srcs/sources_1/new/ALU.v
View File

@@ -9,13 +9,14 @@ module ALU(
// Wires for connecting the modules to the mux
wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H,result_I,result_J,result_K,result_L,result_M,result_N,result_O,result_P;
wire cout;
// A (0000) - Add
add_9bit add0(
.A(operand0),
.B(operand1),
.Cin(1'b0),
.Sum(result_A));
.Sum(result_A),
.Cout(cout));
// B (0001) - Subtract
sub_9bit sub0(
.A(operand0),
@@ -58,7 +59,7 @@ module ALU(
.B(operand1),
.C(result_J));
// K (1010) - Zero
zero zero0(
BEQ zero0(
.A(operand0),
.B(result_K));
// L (1011)
@@ -88,6 +89,8 @@ module ALU(
.P(result_P),
.out(result));
endmodule
//testbench

29
lab2CA.srcs/sources_1/new/BasicModules.v
View File

@@ -270,7 +270,7 @@ module decoder (
2'b01: regOut <= 4'b0010;
2'b10: regOut <= 4'b0100;
2'b11: regOut <= 4'b1000;
default: regOut <= 4'bxxxx;
default: regOut <= 4'b0000;
endcase
end
end
@@ -344,6 +344,21 @@ module mux_2_1(
end
endmodule
module bit1_mux_2_1(
input wire switch,
input wire A,B,
output reg out);
always @(A,B,switch) begin
case (switch)
1'b0 : out = A;
1'b1 : out = B;
default : out = 1'b1;
endcase
end
endmodule
//testbench
module mux_2_1_tb();
reg s;
@@ -519,7 +534,7 @@ module mux_16_1(
input wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,
output reg [8:0] out);
always @(A,B,C,D,E,F,G,H,switch) begin
always @(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,switch) begin
case (switch)
4'b0000 : out = A;
4'b0001 : out = B;
@@ -949,6 +964,7 @@ module sub_9bit(
output wire [8:0] C);
wire [8:0] D;
wire cout;
twos_compliment_9bit two_comp0(
.A(B),
@@ -958,7 +974,8 @@ module sub_9bit(
.A(A),
.B(D),
.Cin(1'b0),
.Sum(C));
.Sum(C),
.Cout(cout));
endmodule
@@ -1011,6 +1028,7 @@ module twos_compliment_9bit(
output wire [8:0] B);
wire [8:0] C;
wire cout;
not_9bit not0(
.A(A),
@@ -1020,7 +1038,8 @@ module twos_compliment_9bit(
.A(C),
.B(9'b000000000),
.Cin(1'b1),
.Sum(B));
.Sum(B),
.Cout(cout));
endmodule
@@ -1053,7 +1072,7 @@ module twos_compliment_tb();
end
endmodule
module zero(
module BEQ(
input wire [8:0] A,
output wire [8:0] B);

29
lab2CA.srcs/sources_1/new/CPU9bits.v
View File

@@ -2,12 +2,13 @@
module CPU9bits(input wire [8:0] instr,
input wire reset, clk,
output reg done
output wire done
);
wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;
wire [2:0] FU, aluOp;
wire addiS, RegEn, loadS;
wire [2:0] FU;
wire [3:0] aluOp;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1;
RegFile RF(
.clk(clk),
@@ -24,7 +25,7 @@ module CPU9bits(input wire [8:0] instr,
FetchUnit FetchU(
.clk(clk),
.reset(reset),
.op_idx(FU[0]),
.op_idx(fetchBranch),
.AddrIn(FUAddr),
.AddrOut(PCout)
);
@@ -43,7 +44,8 @@ module CPU9bits(input wire [8:0] instr,
.FU(FU),
.addi(addiS),
.mem(loadS),
.load(loadMux)
.RegEn(RegEn),
.halt(done)
);
@@ -53,7 +55,8 @@ module CPU9bits(input wire [8:0] instr,
.A(PCout),
.B(JBRes),
.Cin(9'b000000000),
.Sum(FUJB));
.Sum(FUJB),
.Cout(cout0));
mux_2_1 mux1(
.A(op1),
@@ -62,18 +65,25 @@ module CPU9bits(input wire [8:0] instr,
.switch(FU[1]));
mux_2_1 mux2(
.A({4'b0000,instr[4:0]}),
.B({6'b000000,instr[2:0]}),
.A({4'b0000,instr[4:0]}), //Jump
.B({6'b000000,instr[2:0]}),//Branch
.out(JBRes),
.switch(FU[2]));
bit1_mux_2_1 BranMux( // BEQ MUX
.A(FU[0]),
.B(op1[0]),
.out(fetchBranch),
.switch(FU[2])); // FU[2] only goes high when BEQ
///--------------------------Addi Stuff
add_9bit Addier(
.A({6'b000000,instr[2:0]}),
.B(op1),
.Cin(9'b000000000),
.Sum(AddiOut));
.Sum(AddiOut),
.Cout(cout1));
mux_2_1 mux3(
.A(AluOut),
@@ -109,6 +119,7 @@ module CPU9bits_tb();
.done(done));
initial begin
#5
reset = 0;
#10
reset = 1;

35
lab2CA.srcs/sources_1/new/ControlUnit.v
View File

@@ -7,69 +7,88 @@ module ControlUnit(
output reg [2:0] FU,
output reg addi,
output reg mem,
output reg load,
output reg RegEn);
output reg RegEn,
output reg halt);
always @(instIn)begin
always @(instIn, functBit)begin
case(instIn)
4'b0101:
if(functBit == 1) begin
aluOut <= 4'b0001; //sub
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
else begin
aluOut <= 4'b0000; //Add
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
4'b1101: begin
aluOut <= 4'b0011; //nor
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
4'b1110:
if(functBit == 1) begin
aluOut <= 4'b0100; //and
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
else begin
aluOut <= 4'b0010; //or
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
4'b1111:
if(functBit == 1) begin
aluOut <= 4'b0110; //srl
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
else begin
aluOut <= 4'b0101; //shift left
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
4'b0111: begin
aluOut <= 4'b1001; //Less than
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
4'b0110: begin
addi <= 1'b1; // addi
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
4'b1001: begin
4'b1001: begin //We got it wrong, first bit must always be zero whenever branching happens. Fixed
//FU <= 3'b010; // jump
FU <= 3'b010; // jump
RegEn <= 1'b1;
end
4'b1100: begin
FU <= 3'b011; // branch
4'b1010: begin
//FU <= 3'b011; // branch
FU <= 3'b110; // branch
RegEn <= 1'b1;
end
4'b1000: begin
FU <= 3'b001; // jumpreg
//FU <= 3'b001; // jumpreg
FU <= 3'b000; // jumpreg
RegEn <= 1'b1;
end
4'b0001: begin
mem <= 1'b0; // load
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
end
4'b0010: begin
mem <= 1'b1; // store
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
end
4'b0000: begin // regs should initialize at 0, so we shouldn't need to declare it everywhere
halt <= 1'b1; // halt
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
end
default: aluOut <= 4'bxxxx;
endcase
@@ -84,7 +103,6 @@ module ControlUnit_tb();
wire [2:0] FetchUnit;
wire addImmediate;
wire memory;
wire loadIt;
wire RegEnable;
@@ -95,7 +113,6 @@ module ControlUnit_tb();
.FU(FetchUnit),
.addi(addImmediate),
.mem(memory),
.load(loadIt),
.RegEn(RegEnable)
);

4
lab2CA.srcs/sources_1/new/FetchUnit.v
View File

@@ -7,6 +7,7 @@ module FetchUnit(input wire clk, reset,
//Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a)
wire [8:0] progC_out, result_a, result_m;
wire cout;
register PC(
.clk(clk),
@@ -19,7 +20,8 @@ module FetchUnit(input wire clk, reset,
.A(progC_out),
.B(9'b000000001),
.Cin(9'b000000000),
.Sum(AddrOut));
.Sum(AddrOut),
.Cout(cout));
mux_2_1 PCmux(
.A(AddrIn),

2
lab2CA.srcs/sources_1/new/RegFile.v
View File

@@ -41,7 +41,7 @@ module RegFile(input wire clk, reset, enable,
register r3(
.clk(clk),
.reset(reset),
.En(decOut[4]),
.En(decOut[3]),
.Din(write_data),
.Dout(r3_out));