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This commit is contained in:
jose.rodriguezlabra
2019-02-15 12:38:07 -05:00
parent 7aa2cfff2a
commit 0b358a6c41
57 changed files with 3092 additions and 86 deletions
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110
lab2CA.cache/wt/webtalk_pa.xml
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@@ -3,14 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<<<<<<< Updated upstream <application name="pa" timeStamp="Fri Feb 15 12:37:44 2019">
<application name="pa" timeStamp="Fri Feb 8 19:07:41 2019">
=======
<application name="pa" timeStamp="Fri Feb 15 11:20:09 2019">
>>>>>>> Stashed changes
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="a5bb1d0d02704671b324cd827417f368" type="ProjectID"/> <property name="ProjectID" value="c2057eb1fcd843cb85f4e4ade50f1d13" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/> <property name="ProjectIteration" value="2" type="ProjectIteration"/>
</section> </section>
<section name="PlanAhead Usage" visible="true"> <section name="PlanAhead Usage" visible="true">
<item name="Project Data"> <item name="Project Data">
@@ -21,87 +17,47 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/> <property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item> </item>
<item name="Java Command Handlers"> <item name="Java Command Handlers">
<<<<<<< Updated upstream
<property name="AddSources" value="4" type="JavaHandler"/>
<property name="EditDelete" value="1" type="JavaHandler"/>
<property name="NewProject" value="2" type="JavaHandler"/>
<property name="OpenProject" value="2" type="JavaHandler"/>
=======
<property name="AddSources" value="3" type="JavaHandler"/> <property name="AddSources" value="3" type="JavaHandler"/>
<property name="NewProject" value="1" type="JavaHandler"/> <property name="EditDelete" value="1" type="JavaHandler"/>
<property name="OpenProject" value="3" type="JavaHandler"/> <property name="ResetLayout" value="1" type="JavaHandler"/>
>>>>>>> Stashed changes <property name="RunImplementation" value="1" type="JavaHandler"/>
<property name="SaveProjectAs" value="1" type="JavaHandler"/> <property name="RunSchematic" value="4" type="JavaHandler"/>
<property name="RunSynthesis" value="1" type="JavaHandler"/>
<property name="ShowSource" value="1" type="JavaHandler"/>
<property name="SimulationRun" value="1" type="JavaHandler"/>
<property name="ToggleViewNavigator" value="1" type="JavaHandler"/>
<property name="ToolsSettings" value="1" type="JavaHandler"/> <property name="ToolsSettings" value="1" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
<property name="ZoomOut" value="1" type="JavaHandler"/>
</item> </item>
<item name="Gui Handlers"> <item name="Gui Handlers">
<<<<<<< Updated upstream
<property name="BaseDialog_OK" value="7" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_NAME" value="3" type="GuiHandlerData"/>
=======
<property name="BaseDialog_CANCEL" value="1" type="GuiHandlerData"/> <property name="BaseDialog_CANCEL" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="3" type="GuiHandlerData"/> <property name="BaseDialog_OK" value="11" type="GuiHandlerData"/>
<property name="ConfirmSaveTextEditsDialog_NO" value="1" type="GuiHandlerData"/> <property name="CreateSrcFileDialog_FILE_NAME" value="3" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/> <property name="FileSetPanel_FILE_SET_PANEL_TREE" value="72" type="GuiHandlerData"/>
>>>>>>> Stashed changes <property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="13" type="GuiHandlerData"/>
<property name="FPGAChooser_CATEGORY" value="1" type="GuiHandlerData"/> <property name="InstanceMenu_FLOORPLANNING" value="1" type="GuiHandlerData"/>
<property name="FPGAChooser_FAMILY" value="2" type="GuiHandlerData"/> <property name="NetlistTreeView_NETLIST_TREE" value="4" type="GuiHandlerData"/>
<property name="FPGAChooser_FPGA_TABLE" value="1" type="GuiHandlerData"/>
<property name="FPGAChooser_PACKAGE" value="1" type="GuiHandlerData"/>
<<<<<<< Updated upstream
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="36" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="1" type="GuiHandlerData"/>
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="2" type="GuiHandlerData"/>
=======
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="14" type="GuiHandlerData"/>
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
>>>>>>> Stashed changes
<property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_CHECKPOINT" value="3" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="10" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOW" value="12" type="GuiHandlerData"/>
<property name="MainMenuMgr_IP" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="7" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="8" type="GuiHandlerData"/>
<property name="MainMenuMgr_SETTINGS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="16" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_SOURCES" value="3" type="GuiHandlerData"/> <property name="PACommandNames_ADD_SOURCES" value="3" type="GuiHandlerData"/>
<<<<<<< Updated upstream <property name="PACommandNames_AUTO_UPDATE_HIER" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="7" type="GuiHandlerData"/> <property name="PACommandNames_GOTO_IMPLEMENTED_DESIGN" value="1" type="GuiHandlerData"/>
======= <property name="PACommandNames_RUN_BITGEN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="6" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_TIMING" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_SETTINGS" value="1" type="GuiHandlerData"/>
>>>>>>> Stashed changes <property name="PACommandNames_TOGGLE_VIEW_NAV" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SAVE_PROJECT_AS" value="1" type="GuiHandlerData"/> <property name="PACommandNames_ZOOM_OUT" value="1" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="1" type="GuiHandlerData"/> <property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiHandlerData"/>
<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="1" type="GuiHandlerData"/> <property name="PAViews_SCHEMATIC" value="4" type="GuiHandlerData"/>
<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
<property name="RDICommands_CUSTOM_COMMANDS" value="4" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/> <property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
<property name="RDICommands_SETTINGS" value="1" type="GuiHandlerData"/> <property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="2" type="GuiHandlerData"/>
<property name="SettingsProjectGeneralPage_CHOOSE_DEVICE_FOR_YOUR_PROJECT" value="1" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_DIRECTORIES" value="1" type="GuiHandlerData"/>
<<<<<<< Updated upstream
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="1" type="GuiHandlerData"/>
<property name="SrcChooserPanel_CREATE_FILE" value="3" type="GuiHandlerData"/> <property name="SrcChooserPanel_CREATE_FILE" value="3" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="7" type="GuiHandlerData"/> <property name="SrcMenu_IP_HIERARCHY" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="2" type="GuiHandlerData"/>
</item> </item>
<item name="Other"> <item name="Other">
<property name="GuiMode" value="1" type="GuiMode"/> <property name="GuiMode" value="31" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/> <property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="0" type="TclMode"/> <property name="TclMode" value="26" type="TclMode"/>
=======
<property name="SrcChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="6" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="1" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="29" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="24" type="TclMode"/>
>>>>>>> Stashed changes
</item> </item>
</section> </section>
</application> </application>

8
lab2CA.runs/.jobs/vrs_config_1.xml Normal file
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

8
lab2CA.runs/.jobs/vrs_config_2.xml Normal file
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

150
lab2CA.runs/impl_1/RegFile.tcl Normal file
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@@ -0,0 +1,150 @@
#
# Report generation script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
proc start_step { step } {
set stopFile ".stop.rst"
if {[file isfile .stop.rst]} {
puts ""
puts "*** Halting run - EA reset detected ***"
puts ""
puts ""
return -code error
}
set beginFile ".$step.begin.rst"
set platform "$::tcl_platform(platform)"
set user "$::tcl_platform(user)"
set pid [pid]
set host ""
if { [string equal $platform unix] } {
if { [info exist ::env(HOSTNAME)] } {
set host $::env(HOSTNAME)
}
} else {
if { [info exist ::env(COMPUTERNAME)] } {
set host $::env(COMPUTERNAME)
}
}
set ch [open $beginFile w]
puts $ch "<?xml version=\"1.0\"?>"
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
puts $ch " </Process>"
puts $ch "</ProcessHandle>"
close $ch
}
proc end_step { step } {
set endFile ".$step.end.rst"
set ch [open $endFile w]
close $ch
}
proc step_failed { step } {
set endFile ".$step.error.rst"
set ch [open $endFile w]
close $ch
}
start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
create_project -in_memory -part xc7k160tifbg484-2L
set_property design_mode GateLvl [current_fileset]
set_param project.singleFileAddWarning.threshold 0
set_property webtalk.parent_dir {C:/Users/JoseIgnacio/CA Lab/lab2CA.cache/wt} [current_project]
set_property parent.project_path {C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr} [current_project]
set_property ip_output_repo {{C:/Users/JoseIgnacio/CA Lab/lab2CA.cache/ip}} [current_project]
set_property ip_cache_permissions {read write} [current_project]
add_files -quiet {{C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/RegFile.dcp}}
link_design -top RegFile -part xc7k160tifbg484-2L
close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
step_failed init_design
return -code error $RESULT
} else {
end_step init_design
unset ACTIVE_STEP
}
start_step opt_design
set ACTIVE_STEP opt_design
set rc [catch {
create_msg_db opt_design.pb
opt_design
write_checkpoint -force RegFile_opt.dcp
create_report "impl_1_opt_report_drc_0" "report_drc -file RegFile_drc_opted.rpt -pb RegFile_drc_opted.pb -rpx RegFile_drc_opted.rpx"
close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
step_failed opt_design
return -code error $RESULT
} else {
end_step opt_design
unset ACTIVE_STEP
}
start_step place_design
set ACTIVE_STEP place_design
set rc [catch {
create_msg_db place_design.pb
if { [llength [get_debug_cores -quiet] ] > 0 } {
implement_debug_core
}
place_design
write_checkpoint -force RegFile_placed.dcp
create_report "impl_1_place_report_io_0" "report_io -file RegFile_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file RegFile_utilization_placed.rpt -pb RegFile_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file RegFile_control_sets_placed.rpt"
close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
step_failed place_design
return -code error $RESULT
} else {
end_step place_design
unset ACTIVE_STEP
}
start_step route_design
set ACTIVE_STEP route_design
set rc [catch {
create_msg_db route_design.pb
route_design
write_checkpoint -force RegFile_routed.dcp
create_report "impl_1_route_report_drc_0" "report_drc -file RegFile_drc_routed.rpt -pb RegFile_drc_routed.pb -rpx RegFile_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file RegFile_methodology_drc_routed.rpt -pb RegFile_methodology_drc_routed.pb -rpx RegFile_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file RegFile_power_routed.rpt -pb RegFile_power_summary_routed.pb -rpx RegFile_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file RegFile_route_status.rpt -pb RegFile_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file RegFile_timing_summary_routed.rpt -pb RegFile_timing_summary_routed.pb -rpx RegFile_timing_summary_routed.rpx -warn_on_violation "
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file RegFile_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file RegFile_clock_utilization_routed.rpt"
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file RegFile_bus_skew_routed.rpt -pb RegFile_bus_skew_routed.pb -rpx RegFile_bus_skew_routed.rpx"
close_msg_db -file route_design.pb
} RESULT]
if {$rc} {
write_checkpoint -force RegFile_routed_error.dcp
step_failed route_design
return -code error $RESULT
} else {
end_step route_design
unset ACTIVE_STEP
}

380
lab2CA.runs/impl_1/RegFile.vdi Normal file
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@@ -0,0 +1,380 @@
#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Fri Feb 15 12:30:55 2019
# Process ID: 11860
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log RegFile.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source RegFile.tcl -notrace
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/RegFile.vdi
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source RegFile.tcl -notrace
Command: link_design -top RegFile -part xc7k160tifbg484-2L
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Project 1-570] Preparing netlist for logic optimization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 583.539 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 589.113 ; gain = 334.250
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 603.453 ; gain = 14.340
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: aad14af3
Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1128.941 ; gain = 525.488
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: aad14af3
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1225.754 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: aad14af3
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.060 . Memory (MB): peak = 1225.754 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: aad14af3
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1225.754 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: aad14af3
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.071 . Memory (MB): peak = 1225.754 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: aad14af3
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.124 . Memory (MB): peak = 1225.754 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: aad14af3
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.126 . Memory (MB): peak = 1225.754 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 0 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1225.754 ; gain = 0.000
Ending Logic Optimization Task | Checksum: aad14af3
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.129 . Memory (MB): peak = 1225.754 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: aad14af3
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1225.754 ; gain = 0.000
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: aad14af3
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1225.754 ; gain = 0.000
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1225.754 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: aad14af3
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1225.754 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1225.754 ; gain = 636.641
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1225.754 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/RegFile_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file RegFile_drc_opted.rpt -pb RegFile_drc_opted.pb -rpx RegFile_drc_opted.rpx
Command: report_drc -file RegFile_drc_opted.rpt -pb RegFile_drc_opted.pb -rpx RegFile_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/RegFile_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1225.754 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7fa8ebe0
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1225.754 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1225.754 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: ae3aece4
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1238.875 ; gain = 13.121
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 182815a23
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1238.875 ; gain = 13.121
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 182815a23
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1238.875 ; gain = 13.121
Phase 1 Placer Initialization | Checksum: 182815a23
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1238.875 ; gain = 13.121
Phase 2 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1238.875 ; gain = 0.000
Phase 2 Final Placement Cleanup | Checksum: 182815a23
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1238.875 ; gain = 13.121
INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed
Ending Placer Task | Checksum: ae3aece4
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1238.875 ; gain = 13.121
INFO: [Common 17-83] Releasing license: Implementation
38 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1238.875 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.151 . Memory (MB): peak = 1238.875 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/RegFile_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file RegFile_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.112 . Memory (MB): peak = 1243.988 ; gain = 5.113
INFO: [runtcl-4] Executing : report_utilization -file RegFile_utilization_placed.rpt -pb RegFile_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file RegFile_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1243.988 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 2e920104 ConstDB: 0 ShapeSum: 7fa8ebe0 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: ccf0732b
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1467.336 ; gain = 220.660
Post Restoration Checksum: NetGraph: 2e7f4797 NumContArr: 9e712b94 Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: ccf0732b
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1471.402 ; gain = 224.727
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: ccf0732b
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1471.402 ; gain = 224.727
Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: b146062c
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1478.180 ; gain = 231.504
Phase 3 Initial Routing
Number of Nodes with overlaps = 0
Phase 3 Initial Routing | Checksum: b146062c
Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1482.605 ; gain = 235.930
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Phase 4.1 Global Iteration 0 | Checksum: b146062c
Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1482.605 ; gain = 235.930
Phase 4 Rip-up And Reroute | Checksum: b146062c
Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1482.605 ; gain = 235.930
Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: b146062c
Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1482.605 ; gain = 235.930
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: b146062c
Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1482.605 ; gain = 235.930
Phase 6 Post Hold Fix | Checksum: b146062c
Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1482.605 ; gain = 235.930
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0 %
Global Horizontal Routing Utilization = 0 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Congestion Report
North Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: b146062c
Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1482.605 ; gain = 235.930
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: b146062c
Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1484.613 ; gain = 237.938
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: b146062c
Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1484.613 ; gain = 237.938
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1484.613 ; gain = 237.938
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
50 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:33 . Memory (MB): peak = 1484.613 ; gain = 240.625
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1484.613 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.058 . Memory (MB): peak = 1484.613 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/RegFile_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file RegFile_drc_routed.rpt -pb RegFile_drc_routed.pb -rpx RegFile_drc_routed.rpx
Command: report_drc -file RegFile_drc_routed.rpt -pb RegFile_drc_routed.pb -rpx RegFile_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/RegFile_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file RegFile_methodology_drc_routed.rpt -pb RegFile_methodology_drc_routed.pb -rpx RegFile_methodology_drc_routed.rpx
Command: report_methodology -file RegFile_methodology_drc_routed.rpt -pb RegFile_methodology_drc_routed.pb -rpx RegFile_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/RegFile_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file RegFile_power_routed.rpt -pb RegFile_power_summary_routed.pb -rpx RegFile_power_routed.rpx
Command: report_power -file RegFile_power_routed.rpt -pb RegFile_power_summary_routed.pb -rpx RegFile_power_routed.rpx
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
61 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file RegFile_route_status.rpt -pb RegFile_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file RegFile_timing_summary_routed.rpt -pb RegFile_timing_summary_routed.pb -rpx RegFile_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
INFO: [runtcl-4] Executing : report_incremental_reuse -file RegFile_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file RegFile_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file RegFile_bus_skew_routed.rpt -pb RegFile_bus_skew_routed.pb -rpx RegFile_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Fri Feb 15 12:32:12 2019...

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Fri Feb 15 12:32:12 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file RegFile_bus_skew_routed.rpt -pb RegFile_bus_skew_routed.pb -rpx RegFile_bus_skew_routed.rpx
| Design : RegFile
| Device : 7k160ti-fbg484
| Speed File : -2L PRODUCTION 1.12 2017-02-17
------------------------------------------------------------------------------------------------------------------------------------------------------
Bus Skew Report
No bus skew constraints

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Fri Feb 15 12:32:12 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_clock_utilization -file RegFile_clock_utilization_routed.rpt
| Design : RegFile
| Device : 7k160ti-fbg484
| Speed File : -2L PRODUCTION 1.12 2017-02-17
| Temperature Grade : I
------------------------------------------------------------------------------------------
Clock Utilization Report
Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Clock Regions: Key Resource Utilization
5. Clock Regions : Global Clock Summary
1. Clock Primitive Utilization
------------------------------
+----------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 0 | 32 | 0 | 0 | 0 |
| BUFH | 0 | 120 | 0 | 0 | 0 |
| BUFIO | 0 | 32 | 0 | 0 | 0 |
| BUFMR | 0 | 16 | 0 | 0 | 0 |
| BUFR | 0 | 32 | 0 | 0 | 0 |
| MMCM | 0 | 8 | 0 | 0 | 0 |
| PLL | 0 | 8 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
2. Global Clock Resources
-------------------------
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
3. Global Clock Source Details
------------------------------
+-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
4. Clock Regions: Key Resource Utilization
------------------------------------------
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 2150 | 0 | 800 | 0 | 50 | 0 | 25 | 0 | 60 |
| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
| X1Y4 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2300 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
5. Clock Regions : Global Clock Summary
---------------------------------------
All Modules
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y4 | 0 | 0 |
| Y3 | 0 | 0 |
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
# Location of IO Primitives which is load of clock spine
# Location of clock ports

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Fri Feb 15 12:31:34 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file RegFile_control_sets_placed.rpt
| Design : RegFile
| Device : xc7k160ti
------------------------------------------------------------------------------------
Control Set Information
Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information
1. Summary
----------
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets | 0 |
| Unused register locations in slices containing registers | 0 |
+----------------------------------------------------------+-------+
2. Histogram
------------
+--------+--------------+
| Fanout | Control Sets |
+--------+--------------+
3. Flip-Flop Distribution
-------------------------
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 0 | 0 |
| No | No | Yes | 0 | 0 |
| No | Yes | No | 0 | 0 |
| Yes | No | No | 0 | 0 |
| Yes | No | Yes | 0 | 0 |
| Yes | Yes | No | 0 | 0 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+--------------+---------------+------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+--------------+---------------+------------------+------------------+----------------+

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Fri Feb 15 12:31:31 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_drc -file RegFile_drc_opted.rpt -pb RegFile_drc_opted.pb -rpx RegFile_drc_opted.rpx
| Design : RegFile
| Device : xc7k160tifbg484-2L
| Speed File : -2L
| Design State : Synthesized
------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 3
+----------+------------------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+------------------+-----------------------------------------------------+------------+
| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
+----------+------------------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
NSTD-1#1 Critical Warning
Unspecified I/O Standard
18 out of 18 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: op0[8:0], op1[8:0].
Related violations: <none>
UCIO-1#1 Critical Warning
Unconstrained Logical Port
18 out of 18 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: op0[8:0], op1[8:0].
Related violations: <none>
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Fri Feb 15 12:32:09 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_drc -file RegFile_drc_routed.rpt -pb RegFile_drc_routed.pb -rpx RegFile_drc_routed.rpx
| Design : RegFile
| Device : xc7k160tifbg484-2L
| Speed File : -2L
| Design State : Fully Routed
---------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 3
+----------+------------------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+------------------+-----------------------------------------------------+------------+
| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
+----------+------------------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
NSTD-1#1 Critical Warning
Unspecified I/O Standard
18 out of 18 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: op0[8:0], op1[8:0].
Related violations: <none>
UCIO-1#1 Critical Warning
Unconstrained Logical Port
18 out of 18 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: op0[8:0], op1[8:0].
Related violations: <none>
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Fri Feb 15 12:31:34 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_io -file RegFile_io_placed.rpt
| Design : RegFile
| Device : xc7k160ti
| Speed File : -2L
| Package : fbg484
| Package Version : FINAL 2012-06-26
| Package Pin Delay Version : VERS. 2.0 2012-06-26
-------------------------------------------------------------------------------------------------
IO Information
Table of Contents
-----------------
1. Summary
2. IO Assignments by Package Pin
1. Summary
----------
+---------------+
| Total User IO |
+---------------+
| 35 |
+---------------+
2. IO Assignments by Package Pin
--------------------------------
+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| A3 | | | MGTXTXN3_115 | Gigabit | | | | | | | | | | | | | | | |
| A4 | | | MGTXTXP3_115 | Gigabit | | | | | | | | | | | | | | | |
| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A8 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| A9 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| A10 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| A11 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A13 | | High Range | IO_L4P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
| A14 | | High Range | IO_L4N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A15 | | High Range | IO_L9N_T1_DQS_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A16 | | High Range | IO_L8N_T1_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| A18 | | High Range | IO_L10N_T1_AD4N_15 | User IO | | 15 | | | | | | | | | | | | | |
| A19 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | |
| A20 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
| A21 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA1 | | High Performance | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA3 | | High Performance | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AA4 | | High Performance | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AA5 | | High Performance | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA6 | | High Performance | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA7 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| AA8 | | High Performance | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA9 | | High Performance | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA10 | | High Performance | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA11 | | High Performance | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AA13 | | High Performance | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AA14 | op1[5] | High Range | IO_L18P_T2_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| AA15 | op1[4] | High Range | IO_L18N_T2_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| AA16 | op1[7] | High Range | IO_L17P_T2_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| AA18 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA19 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA20 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA21 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB1 | | High Performance | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AB2 | | High Performance | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AB3 | | High Performance | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| AB4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| AB5 | | High Performance | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB6 | | High Performance | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB7 | | High Performance | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB8 | | High Performance | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB10 | | High Performance | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB11 | | High Performance | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB12 | | High Performance | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB13 | | High Performance | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| AB15 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB16 | op1[8] | High Range | IO_L16N_T2_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| AB17 | op1[6] | High Range | IO_L17N_T2_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| AB18 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| AB20 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB21 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| AB22 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| B1 | | | MGTXTXN2_115 | Gigabit | | | | | | | | | | | | | | | |
| B2 | | | MGTXTXP2_115 | Gigabit | | | | | | | | | | | | | | | |
| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B5 | | | MGTXRXN3_115 | Gigabit | | | | | | | | | | | | | | | |
| B6 | | | MGTXRXP3_115 | Gigabit | | | | | | | | | | | | | | | |
| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B8 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B10 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B11 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B12 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
| B13 | | High Range | IO_L5N_T0_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
| B14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| B15 | | High Range | IO_L9P_T1_DQS_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
| B16 | | High Range | IO_L8P_T1_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
| B17 | | High Range | IO_L10P_T1_AD4P_15 | User IO | | 15 | | | | | | | | | | | | | |
| B18 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | |
| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B20 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
| B21 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
| B22 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
| C1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| C3 | | | MGTXRXN2_115 | Gigabit | | | | | | | | | | | | | | | |
| C4 | | | MGTXRXP2_115 | Gigabit | | | | | | | | | | | | | | | |
| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| C7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C8 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| C9 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
| C10 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| C11 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| C12 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C13 | | High Range | IO_L5P_T0_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C14 | | High Range | IO_L7P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C15 | | High Range | IO_L7N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C17 | | High Range | IO_L12P_T1_MRCC_AD5P_15 | User IO | | 15 | | | | | | | | | | | | | |
| C18 | | High Range | IO_L12N_T1_MRCC_AD5N_15 | User IO | | 15 | | | | | | | | | | | | | |
| C19 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | |
| C20 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
| C21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| C22 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
| D1 | | | MGTXTXN1_115 | Gigabit | | | | | | | | | | | | | | | |
| D2 | | | MGTXTXP1_115 | Gigabit | | | | | | | | | | | | | | | |
| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D5 | | | MGTREFCLK0N_115 | Gigabit | | | | | | | | | | | | | | | |
| D6 | | | MGTREFCLK0P_115 | Gigabit | | | | | | | | | | | | | | | |
| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D8 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| D9 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| D10 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| D11 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| D12 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D14 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
| D15 | | High Range | IO_L11P_T1_SRCC_AD12P_15 | User IO | | 15 | | | | | | | | | | | | | |
| D16 | | High Range | IO_L11N_T1_SRCC_AD12N_15 | User IO | | 15 | | | | | | | | | | | | | |
| D17 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| D18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| D19 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | |
| D20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | |
| D21 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| D22 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| E1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| E3 | | | MGTXRXN1_115 | Gigabit | | | | | | | | | | | | | | | |
| E4 | | | MGTXRXP1_115 | Gigabit | | | | | | | | | | | | | | | |
| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E8 | | High Range | IO_24_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| E9 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E11 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| E12 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| E13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| E14 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
| E15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| E16 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| E17 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| E18 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
| E19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | |
| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
| E22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
| F1 | | | MGTXTXN0_115 | Gigabit | | | | | | | | | | | | | | | |
| F2 | | | MGTXTXP0_115 | Gigabit | | | | | | | | | | | | | | | |
| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F5 | | | MGTREFCLK1N_115 | Gigabit | | | | | | | | | | | | | | | |
| F6 | | | MGTREFCLK1P_115 | Gigabit | | | | | | | | | | | | | | | |
| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F8 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| F9 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| F10 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| F11 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| F12 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| F13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| F14 | | High Range | IO_6_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
| F15 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
| F16 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | |
| F19 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
| F20 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
| F21 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
| F22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| G3 | | | MGTXRXN0_115 | Gigabit | | | | | | | | | | | | | | | |
| G4 | | | MGTXRXP0_115 | Gigabit | | | | | | | | | | | | | | | |
| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| G7 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
| G8 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| G9 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| G10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| G11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| G12 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| G13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G15 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
| G16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
| G17 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
| G19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| G20 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
| G21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| G22 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
| H1 | | | MGTAVTTRCAL_115 | Gigabit | | | | | | | | | | | | | | | |
| H2 | | | MGTRREF_115 | Gigabit | | | | | | | | | | | | | | | |
| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H6 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
| H7 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
| H8 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| H9 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| H10 | | High Range | IO_18_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H12 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| H13 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| H14 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
| H15 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
| H17 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
| H18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
| H19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
| H20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H22 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
| J1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J4 | | | MGTVCCAUX | Gigabit Power | | | | | | | | | | | | | | | |
| J5 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
| J6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
| J7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J16 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | |
| J17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | |
| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J19 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
| J20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| J21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
| J22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
| K1 | | High Performance | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K2 | | High Performance | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K3 | | High Performance | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| K4 | | High Performance | IO_0_VRN_34 | User IO | | 34 | | | | | | | | | | | | | |
| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
| K7 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| K11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| K12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K16 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
| K17 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| K18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| K19 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
| K20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| K21 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| K22 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
| L1 | | High Performance | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L3 | | High Performance | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L4 | | High Performance | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
| L5 | | High Performance | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| L6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
| L7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
| L12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
| L13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| L14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L16 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| L18 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
| L19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| L20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| L21 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M1 | | High Performance | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| M2 | | High Performance | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| M3 | | High Performance | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| M4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| M5 | | High Performance | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| M6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
| M7 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| M11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
| M12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M16 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
| M17 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| M18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M20 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
| M21 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
| M22 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| N1 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| N2 | | High Performance | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| N3 | | High Performance | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
| N4 | | High Performance | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| N5 | | High Performance | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| N12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N17 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
| N18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| N19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| N20 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
| N21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| N22 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| P1 | | High Performance | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| P2 | | High Performance | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P4 | | High Performance | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| P5 | | High Performance | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| P6 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
| P7 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
| P8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| P15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P16 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
| P19 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
| P20 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
| P21 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
| P22 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
| R1 | | High Performance | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| R2 | | High Performance | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| R3 | | High Performance | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| R4 | | High Performance | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| R5 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| R6 | | High Performance | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| R7 | | High Performance | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| R16 | op1[1] | High Range | IO_L20P_T3_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| R17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| R18 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
| R19 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| R21 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
| R22 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
| T1 | | High Performance | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| T2 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| T3 | | High Performance | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| T4 | | High Performance | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| T5 | | High Performance | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| T6 | | High Performance | IO_0_VRN_33 | User IO | | 33 | | | | | | | | | | | | | |
| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T8 | | High Performance | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| T9 | | High Performance | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| T10 | | High Performance | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| T11 | | High Performance | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| T12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| T13 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| T14 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | |
| T15 | op0[2] | High Range | IO_L24P_T3_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| T16 | op1[0] | High Range | IO_L20N_T3_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T18 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| T19 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | |
| T20 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| T21 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| T22 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| U1 | | High Performance | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
| U2 | | High Performance | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| U3 | | High Performance | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U5 | | High Performance | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| U6 | | High Performance | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| U7 | | High Performance | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| U8 | | High Performance | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| U9 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| U10 | | High Performance | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| U11 | | High Performance | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| U12 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| U13 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U15 | op0[1] | High Range | IO_L24N_T3_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| U16 | op1[3] | High Range | IO_L19P_T3_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| U17 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| U18 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| U19 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| U20 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
| U21 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| U22 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V2 | | High Performance | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| V3 | | High Performance | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| V4 | | High Performance | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| V5 | | High Performance | IO_25_VRP_34 | User IO | | 34 | | | | | | | | | | | | | |
| V6 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| V7 | | High Performance | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| V8 | | High Performance | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V9 | | High Performance | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| V10 | | High Performance | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V12 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| V13 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| V14 | op0[0] | High Range | IO_25_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| V15 | op0[4] | High Range | IO_L23P_T3_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| V17 | op1[2] | High Range | IO_L19N_T3_VREF_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| V18 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| V19 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| V20 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V22 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| W1 | | High Performance | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| W2 | | High Performance | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| W3 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
| W4 | | High Performance | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| W5 | | High Performance | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| W6 | | High Performance | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| W7 | | High Performance | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W9 | | High Performance | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| W10 | | High Performance | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| W11 | | High Performance | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
| W12 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| W13 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| W14 | op0[6] | High Range | IO_L22P_T3_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| W15 | op0[3] | High Range | IO_L23N_T3_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| W16 | op0[8] | High Range | IO_L21P_T3_DQS_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| W17 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W19 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| W20 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| W21 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| W22 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y1 | | High Performance | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| Y2 | | High Performance | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| Y3 | | High Performance | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| Y4 | | High Performance | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y6 | | High Performance | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y7 | | High Performance | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y8 | | High Performance | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y9 | | High Performance | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y10 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| Y11 | | High Performance | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y12 | | High Performance | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y13 | | High Performance | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
| Y14 | op0[5] | High Range | IO_L22N_T3_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| Y16 | op0[7] | High Range | IO_L21N_T3_DQS_13 | TRISTATE | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| Y17 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y18 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y19 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y20 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| Y21 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
| Y22 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
* Default value
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Fri Feb 15 12:32:11 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_methodology -file RegFile_methodology_drc_routed.rpt -pb RegFile_methodology_drc_routed.pb -rpx RegFile_methodology_drc_routed.rpx
| Design : RegFile
| Device : xc7k160tifbg484-2L
| Speed File : -2L
| Design State : Fully Routed
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Report Methodology
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Max violations: <unlimited>
Violations found: 0
+------+----------+-------------+------------+
| Rule | Severity | Description | Violations |
+------+----------+-------------+------------+
+------+----------+-------------+------------+
2. REPORT DETAILS
-----------------

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Fri Feb 15 12:32:11 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_power -file RegFile_power_routed.rpt -pb RegFile_power_summary_routed.pb -rpx RegFile_power_routed.rpx
| Design : RegFile
| Device : xc7k160tifbg484-2L
| Design State : routed
| Grade : industrial
| Process : typical
| Characterization : Production
-------------------------------------------------------------------------------------------------------------------------------------------
Power Report
Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy
1. Summary
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 0.084 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 0.000 |
| Device Static (W) | 0.084 |
| Effective TJA (C/W) | 2.5 |
| Max Ambient (C) | 99.8 |
| Junction Temperature (C) | 25.2 |
| Confidence Level | High |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
1.1 On-Chip Components
----------------------
+--------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------+-----------+----------+-----------+-----------------+
| Slice Logic | 0.000 | 2 | --- | --- |
| Others | 0.000 | 2 | --- | --- |
| I/O | 0.000 | 18 | 285 | 6.32 |
| Static Power | 0.084 | | | |
| Total | 0.084 | | | |
+--------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
------------------------
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 0.950 | 0.023 | 0.000 | 0.023 |
| Vccaux | 1.800 | 0.016 | 0.000 | 0.016 |
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccbram | 0.950 | 0.001 | 0.000 | 0.001 |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 |
| Vccadc | 1.800 | 0.018 | 0.000 | 0.018 |
+-----------+-------------+-----------+-------------+------------+
1.3 Confidence Level
--------------------
+-----------------------------+------------+------------------------------------------------+--------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+------------------------------------------------+--------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | High | User specified more than 95% of clocks | |
| I/O nodes activity | High | User specified more than 95% of inputs | |
| Internal nodes activity | High | User specified more than 25% of internal nodes | |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | High | | |
+-----------------------------+------------+------------------------------------------------+--------+
2. Settings
-----------
2.1 Environment
---------------
+-----------------------+--------------------------+
| Ambient Temp (C) | 25.0 |
| ThetaJA (C/W) | 2.5 |
| Airflow (LFM) | 250 |
| Heat Sink | medium (Medium Profile) |
| ThetaSA (C/W) | 4.2 |
| Board Selection | medium (10"x10") |
| # of Board Layers | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0 |
+-----------------------+--------------------------+
2.2 Clock Constraints
---------------------
+-------+--------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------+--------+-----------------+
3. Detailed Reports
-------------------
3.1 By Hierarchy
----------------
+------+-----------+
| Name | Power (W) |
+------+-----------+

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Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 20 :
# of nets not needing routing.......... : 18 :
# of internally routed nets........ : 18 :
# of routable nets..................... : 2 :
# of fully routed nets............. : 2 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

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2012.4<EFBFBD>)Timing analysis from Implemented netlist.

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Fri Feb 15 12:32:12 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -file RegFile_timing_summary_routed.rpt -pb RegFile_timing_summary_routed.pb -rpx RegFile_timing_summary_routed.rpx -warn_on_violation
| Design : RegFile
| Device : 7k160ti-fbg484
| Speed File : -2L PRODUCTION 1.12 2017-02-17
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : false
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops
1. checking no_clock
--------------------
There are 0 register/latch pins with no clock.
2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 0 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay
--------------------------
There are 0 input ports with no input delay specified.
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay
---------------------------
There are 0 ports with no output delay specified.
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops
-----------------
There are 0 combinational loops in the design.
10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
NA NA NA NA NA NA NA NA NA NA NA NA
There are no user specified timing constraints.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Fri Feb 15 12:31:34 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_utilization -file RegFile_utilization_placed.rpt -pb RegFile_utilization_placed.pb
| Design : RegFile
| Device : 7k160tifbg484-2L
| Design State : Fully Placed
-----------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs | 0 | 0 | 101400 | 0.00 |
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 0 | 0 | 202800 | 0.00 |
| Register as Flip Flop | 0 | 0 | 202800 | 0.00 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 0 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------------------------------------+------+-------+-----------+-------+
| Slice | 0 | 0 | 25350 | 0.00 |
| SLICEL | 0 | 0 | | |
| SLICEM | 0 | 0 | | |
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 0 | 0 | 202800 | 0.00 |
| Register driven from within the Slice | 0 | | | |
| Register driven from outside the Slice | 0 | | | |
| Unique Control Sets | 0 | | 25350 | 0.00 |
+------------------------------------------+------+-------+-----------+-------+
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 325 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 0 | 0 | 650 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 600 | 0.00 |
+-----------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 18 | 0 | 285 | 6.32 |
| IOB Master Pads | 8 | | | |
| IOB Slave Pads | 9 | | | |
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
| PHASER_REF | 0 | 0 | 8 | 0.00 |
| OUT_FIFO | 0 | 0 | 32 | 0.00 |
| IN_FIFO | 0 | 0 | 32 | 0.00 |
| IDELAYCTRL | 0 | 0 | 8 | 0.00 |
| IBUFDS | 0 | 0 | 275 | 0.00 |
| GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 |
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 285 | 0.00 |
| OLOGIC | 0 | 0 | 285 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
| BUFIO | 0 | 0 | 32 | 0.00 |
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
| BUFMRCE | 0 | 0 | 16 | 0.00 |
| BUFHCE | 0 | 0 | 120 | 0.00 |
| BUFR | 0 | 0 | 32 | 0.00 |
+------------+------+-------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| OBUFT | 18 | IO |
+----------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+

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<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550251846">
<File Type="BITSTR-BMM" Name="RegFile_bd.bmm"/>
<File Type="OPT-METHODOLOGY-DRC" Name="RegFile_methodology_drc_opted.rpt"/>
<File Type="INIT-TIMING" Name="RegFile_timing_summary_init.rpt"/>
<File Type="ROUTE-PWR" Name="RegFile_power_routed.rpt"/>
<File Type="PA-TCL" Name="RegFile.tcl"/>
<File Type="OPT-TIMING" Name="RegFile_timing_summary_opted.rpt"/>
<File Type="OPT-DCP" Name="RegFile_opt.dcp"/>
<File Type="ROUTE-PWR-SUM" Name="RegFile_power_summary_routed.pb"/>
<File Type="REPORTS-TCL" Name="RegFile_reports.tcl"/>
<File Type="OPT-DRC" Name="RegFile_drc_opted.rpt"/>
<File Type="OPT-HWDEF" Name="RegFile.hwdef"/>
<File Type="PWROPT-DCP" Name="RegFile_pwropt.dcp"/>
<File Type="PWROPT-DRC" Name="RegFile_drc_pwropted.rpt"/>
<File Type="PWROPT-TIMING" Name="RegFile_timing_summary_pwropted.rpt"/>
<File Type="PLACE-DCP" Name="RegFile_placed.dcp"/>
<File Type="PLACE-IO" Name="RegFile_io_placed.rpt"/>
<File Type="PLACE-CLK" Name="RegFile_clock_utilization_placed.rpt"/>
<File Type="PLACE-UTIL" Name="RegFile_utilization_placed.rpt"/>
<File Type="PLACE-UTIL-PB" Name="RegFile_utilization_placed.pb"/>
<File Type="PLACE-CTRL" Name="RegFile_control_sets_placed.rpt"/>
<File Type="PLACE-SIMILARITY" Name="RegFile_incremental_reuse_placed.rpt"/>
<File Type="PLACE-PRE-SIMILARITY" Name="RegFile_incremental_reuse_pre_placed.rpt"/>
<File Type="BG-BGN" Name="RegFile.bgn"/>
<File Type="PLACE-TIMING" Name="RegFile_timing_summary_placed.rpt"/>
<File Type="POSTPLACE-PWROPT-DCP" Name="RegFile_postplace_pwropt.dcp"/>
<File Type="BG-BIN" Name="RegFile.bin"/>
<File Type="POSTPLACE-PWROPT-TIMING" Name="RegFile_timing_summary_postplace_pwropted.rpt"/>
<File Type="PHYSOPT-DCP" Name="RegFile_physopt.dcp"/>
<File Type="PHYSOPT-DRC" Name="RegFile_drc_physopted.rpt"/>
<File Type="BITSTR-MSK" Name="RegFile.msk"/>
<File Type="PHYSOPT-TIMING" Name="RegFile_timing_summary_physopted.rpt"/>
<File Type="ROUTE-ERROR-DCP" Name="RegFile_routed_error.dcp"/>
<File Type="ROUTE-DCP" Name="RegFile_routed.dcp"/>
<File Type="ROUTE-BLACKBOX-DCP" Name="RegFile_routed_bb.dcp"/>
<File Type="ROUTE-DRC" Name="RegFile_drc_routed.rpt"/>
<File Type="ROUTE-DRC-PB" Name="RegFile_drc_routed.pb"/>
<File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
<File Type="BITSTR-LTX" Name="RegFile.ltx"/>
<File Type="ROUTE-DRC-RPX" Name="RegFile_drc_routed.rpx"/>
<File Type="BITSTR-MMI" Name="RegFile.mmi"/>
<File Type="ROUTE-METHODOLOGY-DRC" Name="RegFile_methodology_drc_routed.rpt"/>
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="RegFile_methodology_drc_routed.rpx"/>
<File Type="BITSTR-SYSDEF" Name="RegFile.sysdef"/>
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="RegFile_methodology_drc_routed.pb"/>
<File Type="ROUTE-PWR-RPX" Name="RegFile_power_routed.rpx"/>
<File Type="ROUTE-STATUS" Name="RegFile_route_status.rpt"/>
<File Type="ROUTE-STATUS-PB" Name="RegFile_route_status.pb"/>
<File Type="ROUTE-TIMINGSUMMARY" Name="RegFile_timing_summary_routed.rpt"/>
<File Type="ROUTE-TIMING-PB" Name="RegFile_timing_summary_routed.pb"/>
<File Type="ROUTE-TIMING-RPX" Name="RegFile_timing_summary_routed.rpx"/>
<File Type="ROUTE-SIMILARITY" Name="RegFile_incremental_reuse_routed.rpt"/>
<File Type="ROUTE-CLK" Name="RegFile_clock_utilization_routed.rpt"/>
<File Type="ROUTE-BUS-SKEW" Name="RegFile_bus_skew_routed.rpt"/>
<File Type="ROUTE-BUS-SKEW-PB" Name="RegFile_bus_skew_routed.pb"/>
<File Type="ROUTE-BUS-SKEW-RPX" Name="RegFile_bus_skew_routed.rpx"/>
<File Type="POSTROUTE-PHYSOPT-DCP" Name="RegFile_postroute_physopt.dcp"/>
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="RegFile_postroute_physopt_bb.dcp"/>
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="RegFile_timing_summary_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="RegFile_timing_summary_postroute_physopted.pb"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="RegFile_timing_summary_postroute_physopted.rpx"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="RegFile_bus_skew_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="RegFile_bus_skew_postroute_physopted.pb"/>
<File Type="BG-BIT" Name="RegFile.bit"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="RegFile_bus_skew_postroute_physopted.rpx"/>
<File Type="BITSTR-RBT" Name="RegFile.rbt"/>
<File Type="BITSTR-NKY" Name="RegFile.nky"/>
<File Type="BG-DRC" Name="RegFile.drc"/>
<File Type="RDI-RDI" Name="RegFile.vdi"/>
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/FetchUnit.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="RegFile"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
</GenRun>

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REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
REM
vivado -log RegFile.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source RegFile.tcl -notrace

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#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Fri Feb 15 12:30:55 2019
# Process ID: 11860
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log RegFile.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source RegFile.tcl -notrace
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/RegFile.vdi
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source RegFile.tcl -notrace

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lab2CA.runs/synth_1/RegFile.tcl Normal file
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#
# Synthesis run script generated by Vivado
#
set TIME_start [clock seconds]
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
create_project -in_memory -part xc7k160tifbg484-2L
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir {C:/Users/JoseIgnacio/CA Lab/lab2CA.cache/wt} [current_project]
set_property parent.project_path {C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr} [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo {c:/Users/JoseIgnacio/CA Lab/lab2CA.cache/ip} [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_verilog -library xil_defaultlib {
{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v}
{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v}
}
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
set_param ips.enableIPCacheLiteLoad 1
close [open __synthesis_is_running__ w]
synth_design -top RegFile -part xc7k160tifbg484-2L
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef RegFile.dcp
create_report "synth_1_synth_report_utilization_0" "report_utilization -file RegFile_utilization_synth.rpt -pb RegFile_utilization_synth.pb"
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]

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#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Fri Feb 15 12:29:57 2019
# Process ID: 16780
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log RegFile.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source RegFile.tcl
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/RegFile.vds
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source RegFile.tcl -notrace
Command: synth_design -top RegFile -part xc7k160tifbg484-2L
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 1552
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 364.203 ; gain = 101.098
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:23]
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:37]
INFO: [Synth 8-6155] done synthesizing module 'register' (1#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:37]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:60]
INFO: [Synth 8-6157] synthesizing module 'mux' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:57]
INFO: [Synth 8-6155] done synthesizing module 'mux' (2#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:57]
WARNING: [Synth 8-350] instance 'm0' of module 'mux' requires 6 connections, but only 5 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:60]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:67]
WARNING: [Synth 8-350] instance 'm1' of module 'mux' requires 6 connections, but only 5 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:67]
WARNING: [Synth 8-3848] Net op0 in module/entity RegFile does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:26]
WARNING: [Synth 8-3848] Net op1 in module/entity RegFile does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:26]
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:23]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[8]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[7]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[6]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[5]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[4]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[3]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[2]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[1]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[0]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[8]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[7]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[6]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[5]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[4]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[3]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[2]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[1]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[0]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 420.734 ; gain = 157.629
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.734 ; gain = 157.629
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k160tifbg484-2L
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.734 ; gain = 157.629
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.734 ; gain = 157.629
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
No constraint files found.
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 4
+---Muxes :
2 Input 9 Bit Muxes := 4
5 Input 9 Bit Muxes := 2
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module register
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
+---Muxes :
2 Input 9 Bit Muxes := 1
Module mux
Detailed RTL Component Info :
+---Muxes :
5 Input 9 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 600 (col length:100)
BRAMs: 650 (col length: RAMB18 100 RAMB36 50)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
No constraint files found.
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
WARNING: [Synth 8-3330] design RegFile has an empty top module
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[8]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[7]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[6]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[5]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[4]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[3]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[2]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[1]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[0]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[8]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[7]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[6]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[5]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[4]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[3]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[2]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[1]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[0]
WARNING: [Synth 8-3331] design RegFile has unconnected port clk
WARNING: [Synth 8-3331] design RegFile has unconnected port reset
WARNING: [Synth 8-3331] design RegFile has unconnected port write_index[1]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_index[0]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0_idx[1]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0_idx[0]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1_idx[1]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1_idx[0]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[8]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[7]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[6]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[5]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[4]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[3]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[2]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[1]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[0]
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 558.852 ; gain = 295.746
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
No constraint files found.
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 558.852 ; gain = 295.746
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 567.527 ; gain = 304.422
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+------+------+
| |Cell |Count |
+------+------+------+
|1 |OBUFT | 18|
+------+------+------+
Report Instance Areas:
+------+---------+-------+------+
| |Instance |Module |Cells |
+------+---------+-------+------+
|1 |top | | 18|
+------+---------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 60 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 674.148 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
13 Infos, 60 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 674.148 ; gain = 424.316
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 674.148 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/RegFile.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file RegFile_utilization_synth.rpt -pb RegFile_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Fri Feb 15 12:30:22 2019...

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173
lab2CA.runs/synth_1/RegFile_utilization_synth.rpt Normal file
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Fri Feb 15 12:30:22 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_utilization -file RegFile_utilization_synth.rpt -pb RegFile_utilization_synth.pb
| Design : RegFile
| Device : 7k160tifbg484-2L
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 0 | 0 | 101400 | 0.00 |
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 0 | 0 | 202800 | 0.00 |
| Register as Flip Flop | 0 | 0 | 202800 | 0.00 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 0 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 325 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 0 | 0 | 650 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 600 | 0.00 |
+-----------+------+-------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 18 | 0 | 285 | 6.32 |
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
| PHASER_REF | 0 | 0 | 8 | 0.00 |
| OUT_FIFO | 0 | 0 | 32 | 0.00 |
| IN_FIFO | 0 | 0 | 32 | 0.00 |
| IDELAYCTRL | 0 | 0 | 8 | 0.00 |
| IBUFDS | 0 | 0 | 275 | 0.00 |
| GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 |
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 285 | 0.00 |
| OLOGIC | 0 | 0 | 285 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
5. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
| BUFIO | 0 | 0 | 32 | 0.00 |
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
| BUFMRCE | 0 | 0 | 16 | 0.00 |
| BUFHCE | 0 | 0 | 120 | 0.00 |
| BUFR | 0 | 0 | 32 | 0.00 |
+------------+------+-------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
7. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| OBUFT | 18 | IO |
+----------+------+---------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+

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lab2CA.runs/synth_1/gen_run.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550251794">
<File Type="PA-TCL" Name="RegFile.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="RegFile_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="RegFile_reports.tcl"/>
<File Type="RDS-RDS" Name="RegFile.vds"/>
<File Type="RDS-UTIL" Name="RegFile_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="RegFile_utilization_synth.pb"/>
<File Type="RDS-DCP" Name="RegFile.dcp"/>
<File Type="VDS-TIMINGSUMMARY" Name="RegFile_timing_summary_synth.rpt"/>
<File Type="VDS-TIMING-PB" Name="RegFile_timing_summary_synth.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/FetchUnit.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="RegFile"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>

9
lab2CA.runs/synth_1/htr.txt Normal file
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REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
REM
vivado -log RegFile.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source RegFile.tcl

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lab2CA.runs/synth_1/vivado.jou Normal file
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#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Fri Feb 15 12:29:57 2019
# Process ID: 16780
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log RegFile.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source RegFile.tcl
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/RegFile.vds
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source RegFile.tcl -notrace

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11
lab2CA.sim/sim_1/impl/timing/xsim/RegFile.tcl Normal file
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set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns

184
lab2CA.sim/sim_1/impl/timing/xsim/RegFile_time_impl.v Normal file
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// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
// Date : Fri Feb 15 12:36:16 2019
// Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
// Command : write_verilog -mode timesim -nolib -sdf_anno true -force -file {C:/Users/JoseIgnacio/CA
// Lab/lab2CA.sim/sim_1/impl/timing/xsim/RegFile_time_impl.v}
// Design : RegFile
// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or
// synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device : xc7k160tifbg484-2L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING
(* ECO_CHECKSUM = "2b285f13" *)
(* NotValidForBitStream *)
module RegFile
(clk,
reset,
write_index,
op0_idx,
op1_idx,
write_data,
op0,
op1);
input clk;
input reset;
input [1:0]write_index;
input [1:0]op0_idx;
input [1:0]op1_idx;
input [8:0]write_data;
output [8:0]op0;
output [8:0]op1;
wire [8:0]op0;
wire [8:0]op1;
initial begin
$sdf_annotate("RegFile_time_impl.sdf",,,,"tool_control");
end
OBUFT \op0_OBUF[0]_inst
(.I(1'b0),
.O(op0[0]),
.T(1'b1));
OBUFT \op0_OBUF[1]_inst
(.I(1'b0),
.O(op0[1]),
.T(1'b1));
OBUFT \op0_OBUF[2]_inst
(.I(1'b0),
.O(op0[2]),
.T(1'b1));
OBUFT \op0_OBUF[3]_inst
(.I(1'b0),
.O(op0[3]),
.T(1'b1));
OBUFT \op0_OBUF[4]_inst
(.I(1'b0),
.O(op0[4]),
.T(1'b1));
OBUFT \op0_OBUF[5]_inst
(.I(1'b0),
.O(op0[5]),
.T(1'b1));
OBUFT \op0_OBUF[6]_inst
(.I(1'b0),
.O(op0[6]),
.T(1'b1));
OBUFT \op0_OBUF[7]_inst
(.I(1'b0),
.O(op0[7]),
.T(1'b1));
OBUFT \op0_OBUF[8]_inst
(.I(1'b0),
.O(op0[8]),
.T(1'b1));
OBUFT \op1_OBUF[0]_inst
(.I(1'b0),
.O(op1[0]),
.T(1'b1));
OBUFT \op1_OBUF[1]_inst
(.I(1'b0),
.O(op1[1]),
.T(1'b1));
OBUFT \op1_OBUF[2]_inst
(.I(1'b0),
.O(op1[2]),
.T(1'b1));
OBUFT \op1_OBUF[3]_inst
(.I(1'b0),
.O(op1[3]),
.T(1'b1));
OBUFT \op1_OBUF[4]_inst
(.I(1'b0),
.O(op1[4]),
.T(1'b1));
OBUFT \op1_OBUF[5]_inst
(.I(1'b0),
.O(op1[5]),
.T(1'b1));
OBUFT \op1_OBUF[6]_inst
(.I(1'b0),
.O(op1[6]),
.T(1'b1));
OBUFT \op1_OBUF[7]_inst
(.I(1'b0),
.O(op1[7]),
.T(1'b1));
OBUFT \op1_OBUF[8]_inst
(.I(1'b0),
.O(op1[8]),
.T(1'b1));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif

6
lab2CA.sim/sim_1/impl/timing/xsim/RegFile_vlog.prj Normal file
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@@ -0,0 +1,6 @@
# compile verilog/system verilog design source files
verilog xil_defaultlib \
"RegFile_time_impl.v" \
# Do not sort compile order
nosort

12
lab2CA.sim/sim_1/impl/timing/xsim/webtalk.jou Normal file
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@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Fri Feb 15 12:37:49 2019
# Process ID: 17624
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/RegFile_time_impl/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.log
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/JoseIgnacio/CA -notrace

12
lab2CA.sim/sim_1/impl/timing/xsim/webtalk_2004.backup.jou Normal file
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@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Fri Feb 15 12:36:24 2019
# Process ID: 2004
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/RegFile_time_impl/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim/webtalk.log
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/impl/timing/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/JoseIgnacio/CA -notrace

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lab2CA.sim/sim_1/impl/timing/xsim/xelab.pb Normal file
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1
lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/RegFile_time_impl/Compile_Options.txt Normal file
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@@ -0,0 +1 @@
-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" --maxdelay -L "xil_defaultlib" -L "simprims_ver" -L "secureip" --snapshot "RegFile_time_impl" -transport_int_delays -pulse_r "0" -pulse_int_r "0" -pulse_e "0" -pulse_int_e "0" "xil_defaultlib.RegFile" "xil_defaultlib.glbl" -log "elaborate.log"

1
lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/RegFile_time_impl/TempBreakPointFile.txt Normal file
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@@ -0,0 +1 @@
Breakpoint File Version 1.0

148
lab2CA.sim/sim_1/impl/timing/xsim/xsim.dir/RegFile_time_impl/obj/xsim_1.c Normal file
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@@ -0,0 +1,148 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
extern void execute_2(char*, char *);
extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
extern void execute_4(char*, char *);
extern void execute_43(char*, char *);
extern void execute_44(char*, char *);
extern void execute_45(char*, char *);
extern void execute_46(char*, char *);
extern void execute_40(char*, char *);
extern void execute_41(char*, char *);
extern void execute_42(char*, char *);
extern void execute_151(char*, char *);
extern void execute_152(char*, char *);
extern void execute_153(char*, char *);
extern void execute_154(char*, char *);
extern void execute_155(char*, char *);
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
extern void transaction_6(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_7(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_8(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_9(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_10(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_11(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_12(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_13(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_14(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_15(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_16(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_17(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_18(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_19(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_20(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_21(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_22(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_23(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_24(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_25(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_26(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_27(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_28(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_29(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_30(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_31(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_32(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_33(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_34(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_35(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_36(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_37(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_38(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_39(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_40(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_41(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_42(char*, char*, unsigned, unsigned, unsigned);
extern void transaction_43(char*, char*, unsigned, unsigned, unsigned);
funcp funcTab[54] = {(funcp)execute_2, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_4, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_151, (funcp)execute_152, (funcp)execute_153, (funcp)execute_154, (funcp)execute_155, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_6, (funcp)transaction_7, (funcp)transaction_8, (funcp)transaction_9, (funcp)transaction_10, (funcp)transaction_11, (funcp)transaction_12, (funcp)transaction_13, (funcp)transaction_14, (funcp)transaction_15, (funcp)transaction_16, (funcp)transaction_17, (funcp)transaction_18, (funcp)transaction_19, (funcp)transaction_20, (funcp)transaction_21, (funcp)transaction_22, (funcp)transaction_23, (funcp)transaction_24, (funcp)transaction_25, (funcp)transaction_26, (funcp)transaction_27, (funcp)transaction_28, (funcp)transaction_29, (funcp)transaction_30, (funcp)transaction_31, (funcp)transaction_32, (funcp)transaction_33, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_37, (funcp)transaction_38, (funcp)transaction_39, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43};
const int NumRelocateId= 54;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/RegFile_time_impl/xsim.reloc", (void **)funcTab, 54);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/RegFile_time_impl/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/RegFile_time_impl/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern void implicit_HDL_SCinstatiate();
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_sv_type_file_path_name("xsim.dir/RegFile_time_impl/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/RegFile_time_impl/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/RegFile_time_impl/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

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lab2CA.sim/sim_1/impl/timing/xsim/xvlog.pb Normal file
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13
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -24,19 +24,16 @@ module BasicModules();
endmodule endmodule
module gen_clock(); module gen_clock();
reg clk; reg clk;
initial begin initial begin
clk = 1'b0; clk = 1'b0;
end end
always begin always begin
#5 clk = ~clk; // Period to be determined #5 clk = ~clk; // Period to be determined
end end
endmodule endmodule
//To enable register, input 00 to En, register is always outputting contents
module register(input wire clk, reset, module register(input wire clk, reset,
input wire [1:0] En, input wire [1:0] En,
input wire [8:0] Din, input wire [8:0] Din,
@@ -56,6 +53,7 @@ module register(input wire clk, reset,
endmodule endmodule
//Mux follows intuitive switching
module mux(input wire [1:0] switch, module mux(input wire [1:0] switch,
input wire [8:0] A,B,C,D, input wire [8:0] A,B,C,D,
output reg [8:0] out); output reg [8:0] out);
@@ -67,12 +65,15 @@ module mux(input wire [1:0] switch,
else if (switch == 2'b01) begin else if (switch == 2'b01) begin
out = B; out = B;
end end
else if (switch == 2'b11) begin else if (switch == 2'b10) begin
out = C; out = C;
end end
else begin else if (switch == 2'b11) begin
out = D; out = D;
end end
else begin
out = "ZZZZZZZZZ";
end
end end
endmodule endmodule

9
lab2CA.xpr
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@@ -31,7 +31,7 @@
<Option Name="EnableBDX" Val="FALSE"/> <Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/> <Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/> <Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="0"/> <Option Name="WTXSimLaunchSim" Val="1"/>
<Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/>
@@ -102,6 +102,7 @@
<Option Name="TopAutoSet" Val="TRUE"/> <Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/> <Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/> <Option Name="TransportIntDelay" Val="0"/>
<Option Name="SimMode" Val="post-implementation"/>
<Option Name="SrcSet" Val="sources_1"/> <Option Name="SrcSet" Val="sources_1"/>
</Config> </Config>
</FileSet> </FileSet>
@@ -131,15 +132,16 @@
</Simulator> </Simulator>
</Simulators> </Simulators>
<Runs Version="1" Minor="10"> <Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/> <Step Id="synth_design"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/> <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run> </Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/> <Step Id="init_design"/>
@@ -152,6 +154,7 @@
<Step Id="post_route_phys_opt_design"/> <Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/> <Step Id="write_bitstream"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/> <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run> </Run>