Added 1-bit adder

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -1,5 +1,17 @@
 `timescale 1ns / 1ps
 
+module adder_1bit(
+    input wire A,
+    input wire B,
+    input wire Cin,
+    output wire S,
+    output wire Cout);
+
+    assign S = (A ^ B) ^ Cin;
+    assign Cout = ((A ^ B) & Cin) | (A & B);
+
+endmodule
+
 module gen_clock();
 
     reg clk;
@@ -19,6 +31,7 @@ module inverter(
     output wire B);
     
     assign B = ~A;
+
 endmodule
 
 module mux(input wire [1:0] switch,
@@ -33,6 +46,7 @@ module mux(input wire [1:0] switch,
             default: out = D;
         endcase
     end
+
 endmodule
 
 module register(input wire clk, reset,