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Now Asynchronous and recognized by Vivado as RTL_ROM

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WilliamMiceli committed 2019-03-29 16:13:07 -04:00
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commit 5bd244f9ba
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lab2CA.srcs/sources_1/new/instructionMemory.v
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@@ -210,11 +210,8 @@ module instructionMemory(
end
always@(address, clk)begin
if(clk == 1'b1)begin
readData <= memory[address];
end
end
always @ (address)
readData <= memory[address];
endmodule