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Now Asynchronous and recognized by Vivado as RTL_ROM

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WilliamMiceli
2019-03-29 16:13:07 -04:00
parent 5c165d603a
commit 5bd244f9ba
1 changed files with 2 additions and 5 deletions
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5
lab2CA.srcs/sources_1/new/instructionMemory.v
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@@ -210,11 +210,8 @@ module instructionMemory(
end end
always@(address, clk)begin always @ (address)
if(clk == 1'b1)begin
readData <= memory[address]; readData <= memory[address];
end
end
endmodule endmodule