Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts: # Bank_behav1.wcfg # lab2CA.runs/.jobs/vrs_config_42.xml # lab2CA.runs/impl_1/CPU9bits_tb.tcl # lab2CA.runs/impl_1/gen_run.xml # lab2CA.runs/impl_1/htr.txt # lab2CA.runs/impl_1/init_design.pb # lab2CA.runs/impl_1/opt_design.pb # lab2CA.runs/impl_1/place_design.pb # lab2CA.runs/impl_1/vivado.jou # lab2CA.runs/impl_1/vivado.pb # lab2CA.runs/synth_1/CPU9bits.dcp # lab2CA.runs/synth_1/CPU9bits.vds # lab2CA.runs/synth_1/CPU9bits_tb.tcl # lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt # lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb # lab2CA.runs/synth_1/gen_run.xml # lab2CA.runs/synth_1/vivado.jou # lab2CA.runs/synth_1/vivado.pb # lab2CA.sim/sim_1/behav/xsim/webtalk.jou # lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou # lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou # lab2CA.sim/sim_1/behav/xsim/xelab.pb # lab2CA.sim/sim_1/behav/xsim/xvlog.pb # lab2CA.srcs/sources_1/new/instructionMemory.v # lab2CA.xpr
This commit is contained in:
Johannes
@@ -1,153 +0,0 @@
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#
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||||
# Report generation script generated by Vivado
|
||||
#
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
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||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
proc start_step { step } {
|
||||
set stopFile ".stop.rst"
|
||||
if {[file isfile .stop.rst]} {
|
||||
puts ""
|
||||
puts "*** Halting run - EA reset detected ***"
|
||||
puts ""
|
||||
puts ""
|
||||
return -code error
|
||||
}
|
||||
set beginFile ".$step.begin.rst"
|
||||
set platform "$::tcl_platform(platform)"
|
||||
set user "$::tcl_platform(user)"
|
||||
set pid [pid]
|
||||
set host ""
|
||||
if { [string equal $platform unix] } {
|
||||
if { [info exist ::env(HOSTNAME)] } {
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||||
set host $::env(HOSTNAME)
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||||
}
|
||||
} else {
|
||||
if { [info exist ::env(COMPUTERNAME)] } {
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||||
set host $::env(COMPUTERNAME)
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||||
}
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||||
}
|
||||
set ch [open $beginFile w]
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puts $ch "<?xml version=\"1.0\"?>"
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puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
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||||
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
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puts $ch " </Process>"
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puts $ch "</ProcessHandle>"
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close $ch
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}
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||||
|
||||
proc end_step { step } {
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||||
set endFile ".$step.end.rst"
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set ch [open $endFile w]
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||||
close $ch
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||||
}
|
||||
|
||||
proc step_failed { step } {
|
||||
set endFile ".$step.error.rst"
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||||
set ch [open $endFile w]
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close $ch
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}
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||||
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||||
set_msg_config -id {Synth 8-256} -limit 10000
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set_msg_config -id {Synth 8-638} -limit 10000
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|
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start_step init_design
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set ACTIVE_STEP init_design
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set rc [catch {
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||||
create_msg_db init_design.pb
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||||
set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-784-DESKTOP-8QFGS52/incrSyn
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create_project -in_memory -part xc7k160tifbg484-2L
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set_property design_mode GateLvl [current_fileset]
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set_param project.singleFileAddWarning.threshold 0
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||||
set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project]
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set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project]
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||||
set_property ip_output_repo C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project]
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set_property ip_cache_permissions {read write} [current_project]
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add_files -quiet C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.dcp
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link_design -top CPU9bits_tb -part xc7k160tifbg484-2L
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close_msg_db -file init_design.pb
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} RESULT]
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||||
if {$rc} {
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||||
step_failed init_design
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return -code error $RESULT
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} else {
|
||||
end_step init_design
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||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
start_step opt_design
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set ACTIVE_STEP opt_design
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||||
set rc [catch {
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||||
create_msg_db opt_design.pb
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opt_design
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write_checkpoint -force CPU9bits_tb_opt.dcp
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create_report "impl_1_opt_report_drc_0" "report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx"
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close_msg_db -file opt_design.pb
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} RESULT]
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||||
if {$rc} {
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||||
step_failed opt_design
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return -code error $RESULT
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} else {
|
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end_step opt_design
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unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
start_step place_design
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set ACTIVE_STEP place_design
|
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set rc [catch {
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create_msg_db place_design.pb
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||||
if { [llength [get_debug_cores -quiet] ] > 0 } {
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||||
implement_debug_core
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}
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place_design
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write_checkpoint -force CPU9bits_tb_placed.dcp
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create_report "impl_1_place_report_io_0" "report_io -file CPU9bits_tb_io_placed.rpt"
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create_report "impl_1_place_report_utilization_0" "report_utilization -file CPU9bits_tb_utilization_placed.rpt -pb CPU9bits_tb_utilization_placed.pb"
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create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file CPU9bits_tb_control_sets_placed.rpt"
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close_msg_db -file place_design.pb
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} RESULT]
|
||||
if {$rc} {
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||||
step_failed place_design
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return -code error $RESULT
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} else {
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||||
end_step place_design
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unset ACTIVE_STEP
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||||
}
|
||||
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||||
start_step route_design
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set ACTIVE_STEP route_design
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set rc [catch {
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||||
create_msg_db route_design.pb
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||||
route_design
|
||||
write_checkpoint -force CPU9bits_tb_routed.dcp
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||||
create_report "impl_1_route_report_drc_0" "report_drc -file CPU9bits_tb_drc_routed.rpt -pb CPU9bits_tb_drc_routed.pb -rpx CPU9bits_tb_drc_routed.rpx"
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create_report "impl_1_route_report_methodology_0" "report_methodology -file CPU9bits_tb_methodology_drc_routed.rpt -pb CPU9bits_tb_methodology_drc_routed.pb -rpx CPU9bits_tb_methodology_drc_routed.rpx"
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||||
create_report "impl_1_route_report_power_0" "report_power -file CPU9bits_tb_power_routed.rpt -pb CPU9bits_tb_power_summary_routed.pb -rpx CPU9bits_tb_power_routed.rpx"
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||||
create_report "impl_1_route_report_route_status_0" "report_route_status -file CPU9bits_tb_route_status.rpt -pb CPU9bits_tb_route_status.pb"
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||||
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file CPU9bits_tb_timing_summary_routed.rpt -pb CPU9bits_tb_timing_summary_routed.pb -rpx CPU9bits_tb_timing_summary_routed.rpx -warn_on_violation "
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||||
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file CPU9bits_tb_incremental_reuse_routed.rpt"
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||||
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file CPU9bits_tb_clock_utilization_routed.rpt"
|
||||
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file CPU9bits_tb_bus_skew_routed.rpt -pb CPU9bits_tb_bus_skew_routed.pb -rpx CPU9bits_tb_bus_skew_routed.rpx"
|
||||
close_msg_db -file route_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
write_checkpoint -force CPU9bits_tb_routed_error.dcp
|
||||
step_failed route_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step route_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
@@ -1,167 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1553466509">
|
||||
<File Type="BITSTR-BMM" Name="CPU9bits_tb_bd.bmm"/>
|
||||
<File Type="OPT-METHODOLOGY-DRC" Name="CPU9bits_tb_methodology_drc_opted.rpt"/>
|
||||
<File Type="INIT-TIMING" Name="CPU9bits_tb_timing_summary_init.rpt"/>
|
||||
<File Type="ROUTE-PWR" Name="CPU9bits_tb_power_routed.rpt"/>
|
||||
<File Type="PA-TCL" Name="CPU9bits_tb.tcl"/>
|
||||
<File Type="OPT-TIMING" Name="CPU9bits_tb_timing_summary_opted.rpt"/>
|
||||
<File Type="OPT-DCP" Name="CPU9bits_tb_opt.dcp"/>
|
||||
<File Type="ROUTE-PWR-SUM" Name="CPU9bits_tb_power_summary_routed.pb"/>
|
||||
<File Type="REPORTS-TCL" Name="CPU9bits_tb_reports.tcl"/>
|
||||
<File Type="OPT-DRC" Name="CPU9bits_tb_drc_opted.rpt"/>
|
||||
<File Type="OPT-HWDEF" Name="CPU9bits_tb.hwdef"/>
|
||||
<File Type="PWROPT-DCP" Name="CPU9bits_tb_pwropt.dcp"/>
|
||||
<File Type="PWROPT-DRC" Name="CPU9bits_tb_drc_pwropted.rpt"/>
|
||||
<File Type="PWROPT-TIMING" Name="CPU9bits_tb_timing_summary_pwropted.rpt"/>
|
||||
<File Type="PLACE-DCP" Name="CPU9bits_tb_placed.dcp"/>
|
||||
<File Type="PLACE-IO" Name="CPU9bits_tb_io_placed.rpt"/>
|
||||
<File Type="PLACE-CLK" Name="CPU9bits_tb_clock_utilization_placed.rpt"/>
|
||||
<File Type="PLACE-UTIL" Name="CPU9bits_tb_utilization_placed.rpt"/>
|
||||
<File Type="PLACE-UTIL-PB" Name="CPU9bits_tb_utilization_placed.pb"/>
|
||||
<File Type="PLACE-CTRL" Name="CPU9bits_tb_control_sets_placed.rpt"/>
|
||||
<File Type="PLACE-SIMILARITY" Name="CPU9bits_tb_incremental_reuse_placed.rpt"/>
|
||||
<File Type="PLACE-PRE-SIMILARITY" Name="CPU9bits_tb_incremental_reuse_pre_placed.rpt"/>
|
||||
<File Type="BG-BGN" Name="CPU9bits_tb.bgn"/>
|
||||
<File Type="PLACE-TIMING" Name="CPU9bits_tb_timing_summary_placed.rpt"/>
|
||||
<File Type="POSTPLACE-PWROPT-DCP" Name="CPU9bits_tb_postplace_pwropt.dcp"/>
|
||||
<File Type="BG-BIN" Name="CPU9bits_tb.bin"/>
|
||||
<File Type="POSTPLACE-PWROPT-TIMING" Name="CPU9bits_tb_timing_summary_postplace_pwropted.rpt"/>
|
||||
<File Type="PHYSOPT-DCP" Name="CPU9bits_tb_physopt.dcp"/>
|
||||
<File Type="PHYSOPT-DRC" Name="CPU9bits_tb_drc_physopted.rpt"/>
|
||||
<File Type="BITSTR-MSK" Name="CPU9bits_tb.msk"/>
|
||||
<File Type="PHYSOPT-TIMING" Name="CPU9bits_tb_timing_summary_physopted.rpt"/>
|
||||
<File Type="ROUTE-ERROR-DCP" Name="CPU9bits_tb_routed_error.dcp"/>
|
||||
<File Type="ROUTE-DCP" Name="CPU9bits_tb_routed.dcp"/>
|
||||
<File Type="ROUTE-BLACKBOX-DCP" Name="CPU9bits_tb_routed_bb.dcp"/>
|
||||
<File Type="ROUTE-DRC" Name="CPU9bits_tb_drc_routed.rpt"/>
|
||||
<File Type="ROUTE-DRC-PB" Name="CPU9bits_tb_drc_routed.pb"/>
|
||||
<File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
|
||||
<File Type="BITSTR-LTX" Name="CPU9bits_tb.ltx"/>
|
||||
<File Type="ROUTE-DRC-RPX" Name="CPU9bits_tb_drc_routed.rpx"/>
|
||||
<File Type="BITSTR-MMI" Name="CPU9bits_tb.mmi"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC" Name="CPU9bits_tb_methodology_drc_routed.rpt"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="CPU9bits_tb_methodology_drc_routed.rpx"/>
|
||||
<File Type="BITSTR-SYSDEF" Name="CPU9bits_tb.sysdef"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="CPU9bits_tb_methodology_drc_routed.pb"/>
|
||||
<File Type="ROUTE-PWR-RPX" Name="CPU9bits_tb_power_routed.rpx"/>
|
||||
<File Type="ROUTE-STATUS" Name="CPU9bits_tb_route_status.rpt"/>
|
||||
<File Type="ROUTE-STATUS-PB" Name="CPU9bits_tb_route_status.pb"/>
|
||||
<File Type="ROUTE-TIMINGSUMMARY" Name="CPU9bits_tb_timing_summary_routed.rpt"/>
|
||||
<File Type="ROUTE-TIMING-PB" Name="CPU9bits_tb_timing_summary_routed.pb"/>
|
||||
<File Type="ROUTE-TIMING-RPX" Name="CPU9bits_tb_timing_summary_routed.rpx"/>
|
||||
<File Type="ROUTE-SIMILARITY" Name="CPU9bits_tb_incremental_reuse_routed.rpt"/>
|
||||
<File Type="ROUTE-CLK" Name="CPU9bits_tb_clock_utilization_routed.rpt"/>
|
||||
<File Type="ROUTE-BUS-SKEW" Name="CPU9bits_tb_bus_skew_routed.rpt"/>
|
||||
<File Type="ROUTE-BUS-SKEW-PB" Name="CPU9bits_tb_bus_skew_routed.pb"/>
|
||||
<File Type="ROUTE-BUS-SKEW-RPX" Name="CPU9bits_tb_bus_skew_routed.rpx"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-DCP" Name="CPU9bits_tb_postroute_physopt.dcp"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="CPU9bits_tb_postroute_physopt_bb.dcp"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="CPU9bits_tb_timing_summary_postroute_physopted.rpt"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="CPU9bits_tb_timing_summary_postroute_physopted.pb"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="CPU9bits_tb_timing_summary_postroute_physopted.rpx"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="CPU9bits_tb_bus_skew_postroute_physopted.rpt"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="CPU9bits_tb_bus_skew_postroute_physopted.pb"/>
|
||||
<File Type="BG-BIT" Name="CPU9bits_tb.bit"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="CPU9bits_tb_bus_skew_postroute_physopted.rpx"/>
|
||||
<File Type="BITSTR-RBT" Name="CPU9bits_tb.rbt"/>
|
||||
<File Type="BITSTR-NKY" Name="CPU9bits_tb.nky"/>
|
||||
<File Type="BG-DRC" Name="CPU9bits_tb.drc"/>
|
||||
<File Type="RDI-RDI" Name="CPU9bits_tb.vdi"/>
|
||||
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ControlUnit.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/FetchUnit.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/dataMemory.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/instructionMemory.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/CPU9bits.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="CPU9bits_tb"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
@@ -1,9 +0,0 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log CPU9bits_tb.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits_tb.tcl -notrace
|
||||
Reference in New Issue
Block a user