Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts: # Bank_behav1.wcfg # lab2CA.runs/.jobs/vrs_config_42.xml # lab2CA.runs/impl_1/CPU9bits_tb.tcl # lab2CA.runs/impl_1/gen_run.xml # lab2CA.runs/impl_1/htr.txt # lab2CA.runs/impl_1/init_design.pb # lab2CA.runs/impl_1/opt_design.pb # lab2CA.runs/impl_1/place_design.pb # lab2CA.runs/impl_1/vivado.jou # lab2CA.runs/impl_1/vivado.pb # lab2CA.runs/synth_1/CPU9bits.dcp # lab2CA.runs/synth_1/CPU9bits.vds # lab2CA.runs/synth_1/CPU9bits_tb.tcl # lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt # lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb # lab2CA.runs/synth_1/gen_run.xml # lab2CA.runs/synth_1/vivado.jou # lab2CA.runs/synth_1/vivado.pb # lab2CA.sim/sim_1/behav/xsim/webtalk.jou # lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou # lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou # lab2CA.sim/sim_1/behav/xsim/xelab.pb # lab2CA.sim/sim_1/behav/xsim/xvlog.pb # lab2CA.srcs/sources_1/new/instructionMemory.v # lab2CA.xpr
This commit is contained in:
Johannes
BIN
lab2CA.runs/synth_1/CPU9bits.dcp
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lab2CA.runs/synth_1/CPU9bits.dcp
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lab2CA.runs/synth_1/CPU9bits.vds
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lab2CA.runs/synth_1/CPU9bits.vds
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#-----------------------------------------------------------
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# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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||||
# Start of session at: Sun Mar 24 16:57:48 2019
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# Process ID: 9320
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||||
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1
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# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
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# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
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||||
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
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||||
#-----------------------------------------------------------
|
||||
source CPU9bits.tcl -notrace
|
||||
Command: synth_design -top CPU9bits -part xc7k160tifbg484-2L
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
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||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 4932
|
||||
WARNING: [Synth 8-1958] event expressions must result in a singular type [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:81]
|
||||
---------------------------------------------------------------------------------
|
||||
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 376.207 ; gain = 113.672
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||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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||||
INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
|
||||
WARNING: [Synth 8-567] referenced signal 'writeEnable' should be on the sensitivity list [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:81]
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||||
WARNING: [Synth 8-567] referenced signal 'writeData' should be on the sensitivity list [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:81]
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||||
INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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||||
INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
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||||
INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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||||
INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
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||||
INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
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||||
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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||||
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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||||
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
|
||||
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
|
||||
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
|
||||
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
|
||||
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
|
||||
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
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||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
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||||
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
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||||
INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
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||||
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
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||||
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
|
||||
WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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||||
WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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||||
WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
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||||
INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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||||
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
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||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:17]
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||||
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
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||||
INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
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||||
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
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||||
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
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||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
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||||
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (27#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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||||
WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0]
|
||||
WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0]
|
||||
WARNING: [Synth 8-3331] design shift_left has unconnected port A[8]
|
||||
WARNING: [Synth 8-3331] design instructionMemory has unconnected port clk
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 414.008 ; gain = 151.473
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 414.008 ; gain = 151.473
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k160tifbg484-2L
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 414.008 ; gain = 151.473
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[15]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[14]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[13]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[12]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[11]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[10]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[9]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[8]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[7]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[6]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[5]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[4]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[3]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[2]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[1]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[0]' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:83]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'dataMemEn_reg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:26]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 461.227 ; gain = 198.691
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-223] decloning instance 'SE1' (sign_extend_3bit) to 'SE3'
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 162
|
||||
+---Registers :
|
||||
9 Bit Registers := 9
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 28
|
||||
4 Input 9 Bit Muxes := 4
|
||||
2 Input 4 Bit Muxes := 2
|
||||
4 Input 4 Bit Muxes := 2
|
||||
16 Input 4 Bit Muxes := 1
|
||||
2 Input 3 Bit Muxes := 2
|
||||
16 Input 3 Bit Muxes := 1
|
||||
16 Input 2 Bit Muxes := 1
|
||||
16 Input 1 Bit Muxes := 24
|
||||
2 Input 1 Bit Muxes := 33
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module dataMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 20
|
||||
16 Input 1 Bit Muxes := 16
|
||||
2 Input 1 Bit Muxes := 32
|
||||
Module decoder
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 4 Bit Muxes := 1
|
||||
4 Input 4 Bit Muxes := 1
|
||||
Module register
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
Module mux_4_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
4 Input 9 Bit Muxes := 1
|
||||
Module add_1bit
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module mux_2_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 1
|
||||
Module ControlUnit
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
16 Input 4 Bit Muxes := 1
|
||||
2 Input 3 Bit Muxes := 2
|
||||
16 Input 3 Bit Muxes := 1
|
||||
16 Input 2 Bit Muxes := 1
|
||||
16 Input 1 Bit Muxes := 8
|
||||
Module bit1_mux_2_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 600 (col length:100)
|
||||
BRAMs: 650 (col length: RAMB18 100 RAMB36 50)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
ROM:
|
||||
+------------------+------------+---------------+----------------+
|
||||
|Module Name | RTL Object | Depth x Width | Implemented As |
|
||||
+------------------+------------+---------------+----------------+
|
||||
|instructionMemory | p_0_out | 64x9 | LUT |
|
||||
|CPU9bits | p_0_out | 64x9 | LUT |
|
||||
+------------------+------------+---------------+----------------+
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
Finished ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+------+------+
|
||||
| |Cell |Count |
|
||||
+------+------+------+
|
||||
|1 |BUFG | 2|
|
||||
|2 |LUT2 | 45|
|
||||
|3 |LUT3 | 50|
|
||||
|4 |LUT4 | 51|
|
||||
|5 |LUT5 | 69|
|
||||
|6 |LUT6 | 439|
|
||||
|7 |MUXF7 | 6|
|
||||
|8 |FDRE | 81|
|
||||
|9 |LD | 154|
|
||||
|10 |IBUF | 2|
|
||||
|11 |OBUF | 1|
|
||||
+------+------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+------------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+------------+------+
|
||||
|1 |top | | 900|
|
||||
|2 | Bank |RegFile | 45|
|
||||
|3 | r0 |register_5 | 16|
|
||||
|4 | r1 |register_6 | 9|
|
||||
|5 | r2 |register_7 | 10|
|
||||
|6 | r3 |register_8 | 10|
|
||||
|7 | CU |ControlUnit | 14|
|
||||
|8 | FetchU |FetchUnit | 126|
|
||||
|9 | PC |register_4 | 126|
|
||||
|10 | RF |RegFile_0 | 345|
|
||||
|11 | r0 |register | 216|
|
||||
|12 | r1 |register_1 | 14|
|
||||
|13 | r2 |register_2 | 100|
|
||||
|14 | r3 |register_3 | 15|
|
||||
|15 | dM |dataMemory | 365|
|
||||
+------+---------+------------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 29 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 723.004 ; gain = 460.469
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 160 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 723.004 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 154 instances were transformed.
|
||||
LD => LDCE: 154 instances
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
70 Infos, 29 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 723.004 ; gain = 473.363
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 723.004 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Sun Mar 24 16:58:31 2019...
|
||||
@@ -17,7 +17,7 @@ proc create_report { reportName command } {
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-784-DESKTOP-8QFGS52/incrSyn
|
||||
set_param synth.incrementalSynthesisCache C:/Users/willi/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-18452-WM-G75VW/incrSyn
|
||||
set_msg_config -id {Synth 8-256} -limit 10000
|
||||
set_msg_config -id {Synth 8-638} -limit 10000
|
||||
create_project -in_memory -part xc7k160tifbg484-2L
|
||||
@@ -25,21 +25,21 @@ create_project -in_memory -part xc7k160tifbg484-2L
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project]
|
||||
set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project]
|
||||
set_property webtalk.parent_dir {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/wt} [current_project]
|
||||
set_property parent.project_path {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo c:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project]
|
||||
set_property ip_output_repo {c:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/ip} [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_verilog -library xil_defaultlib {
|
||||
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v
|
||||
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v
|
||||
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v
|
||||
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v
|
||||
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v
|
||||
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v
|
||||
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v
|
||||
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v
|
||||
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v}
|
||||
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v}
|
||||
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v}
|
||||
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v}
|
||||
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v}
|
||||
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v}
|
||||
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v}
|
||||
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v}
|
||||
}
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
@@ -52,12 +52,12 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top CPU9bits_tb -part xc7k160tifbg484-2L
|
||||
synth_design -top CPU9bits -part xc7k160tifbg484-2L
|
||||
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef CPU9bits_tb.dcp
|
||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file CPU9bits_tb_utilization_synth.rpt -pb CPU9bits_tb_utilization_synth.pb"
|
||||
write_checkpoint -force -noxdef CPU9bits.dcp
|
||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb"
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------------------
|
||||
-----------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Sun Mar 24 18:38:37 2019
|
||||
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file CPU9bits_tb_utilization_synth.rpt -pb CPU9bits_tb_utilization_synth.pb
|
||||
| Design : CPU9bits_tb
|
||||
| Date : Sun Mar 24 16:58:30 2019
|
||||
| Host : WM-G75VW running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
| Design : CPU9bits
|
||||
| Device : 7k160tifbg484-2L
|
||||
| Design State : Fully Placed
|
||||
-----------------------------------------------------------------------------------------------------------------
|
||||
| Design State : Synthesized
|
||||
-----------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
@@ -15,15 +15,14 @@ Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Slice Logic Distribution
|
||||
3. Memory
|
||||
4. DSP
|
||||
5. IO and GT Specific
|
||||
6. Clocking
|
||||
7. Specific Feature
|
||||
8. Primitives
|
||||
9. Black Boxes
|
||||
10. Instantiated Netlists
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
@@ -31,15 +30,16 @@ Table of Contents
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs | 0 | 0 | 101400 | 0.00 |
|
||||
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
|
||||
| Slice LUTs* | 578 | 0 | 101400 | 0.57 |
|
||||
| LUT as Logic | 578 | 0 | 101400 | 0.57 |
|
||||
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
|
||||
| Slice Registers | 0 | 0 | 202800 | 0.00 |
|
||||
| Register as Flip Flop | 0 | 0 | 202800 | 0.00 |
|
||||
| Register as Latch | 0 | 0 | 202800 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
|
||||
| Slice Registers | 235 | 0 | 202800 | 0.12 |
|
||||
| Register as Flip Flop | 81 | 0 | 202800 | 0.04 |
|
||||
| Register as Latch | 154 | 0 | 202800 | 0.08 |
|
||||
| F7 Muxes | 6 | 0 | 50700 | 0.01 |
|
||||
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
@@ -55,34 +55,13 @@ Table of Contents
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 154 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 0 | Yes | Reset | - |
|
||||
| 81 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Slice Logic Distribution
|
||||
---------------------------
|
||||
|
||||
+------------------------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------------------------------------+------+-------+-----------+-------+
|
||||
| Slice | 0 | 0 | 25350 | 0.00 |
|
||||
| SLICEL | 0 | 0 | | |
|
||||
| SLICEM | 0 | 0 | | |
|
||||
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
|
||||
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
|
||||
| LUT as Distributed RAM | 0 | 0 | | |
|
||||
| LUT as Shift Register | 0 | 0 | | |
|
||||
| Slice Registers | 0 | 0 | 202800 | 0.00 |
|
||||
| Register driven from within the Slice | 0 | | | |
|
||||
| Register driven from outside the Slice | 0 | | | |
|
||||
| Unique Control Sets | 0 | | 25350 | 0.00 |
|
||||
+------------------------------------------+------+-------+-----------+-------+
|
||||
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
|
||||
|
||||
|
||||
3. Memory
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
@@ -95,7 +74,7 @@ Table of Contents
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
4. DSP
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
@@ -105,13 +84,13 @@ Table of Contents
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. IO and GT Specific
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 0 | 0 | 285 | 0.00 |
|
||||
| Bonded IOB | 3 | 0 | 285 | 1.05 |
|
||||
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
|
||||
@@ -132,13 +111,13 @@ Table of Contents
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Clocking
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFGCTRL | 2 | 0 | 32 | 6.25 |
|
||||
| BUFIO | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
@@ -148,7 +127,7 @@ Table of Contents
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Specific Feature
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
@@ -166,15 +145,27 @@ Table of Contents
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
8. Primitives
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| LUT6 | 439 | LUT |
|
||||
| LDCE | 154 | Flop & Latch |
|
||||
| FDRE | 81 | Flop & Latch |
|
||||
| LUT5 | 69 | LUT |
|
||||
| LUT4 | 51 | LUT |
|
||||
| LUT3 | 50 | LUT |
|
||||
| LUT2 | 45 | LUT |
|
||||
| MUXF7 | 6 | MuxFx |
|
||||
| IBUF | 2 | IO |
|
||||
| BUFG | 2 | Clock |
|
||||
| OBUF | 1 | IO |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
9. Black Boxes
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
@@ -182,8 +173,8 @@ Table of Contents
|
||||
+----------+------+
|
||||
|
||||
|
||||
10. Instantiated Netlists
|
||||
-------------------------
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
|
||||
BIN
lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
Normal file
BIN
lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
Normal file
Binary file not shown.
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1553466509">
|
||||
<File Type="PA-TCL" Name="CPU9bits_tb.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="CPU9bits_tb_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="CPU9bits_tb_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="CPU9bits_tb.vds"/>
|
||||
<File Type="RDS-UTIL" Name="CPU9bits_tb_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="CPU9bits_tb_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="CPU9bits_tb.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="CPU9bits_tb_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="CPU9bits_tb_timing_summary_synth.pb"/>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1553461063">
|
||||
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="CPU9bits.vds"/>
|
||||
<File Type="RDS-UTIL" Name="CPU9bits_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="CPU9bits_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="CPU9bits.dcp"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
@@ -77,7 +74,7 @@
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="CPU9bits_tb"/>
|
||||
<Option Name="TopModule" Val="CPU9bits"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
|
||||
@@ -2,11 +2,11 @@
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Sun Mar 24 18:28:31 2019
|
||||
# Process ID: 5228
|
||||
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log CPU9bits_tb.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl
|
||||
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.vds
|
||||
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
# Start of session at: Sun Mar 24 16:57:48 2019
|
||||
# Process ID: 9320
|
||||
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
|
||||
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
|
||||
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source CPU9bits_tb.tcl -notrace
|
||||
source CPU9bits.tcl -notrace
|
||||
|
||||
Reference in New Issue
Block a user