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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

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# Conflicts:
#	Bank_behav1.wcfg
#	lab2CA.runs/.jobs/vrs_config_42.xml
#	lab2CA.runs/impl_1/CPU9bits_tb.tcl
#	lab2CA.runs/impl_1/gen_run.xml
#	lab2CA.runs/impl_1/htr.txt
#	lab2CA.runs/impl_1/init_design.pb
#	lab2CA.runs/impl_1/opt_design.pb
#	lab2CA.runs/impl_1/place_design.pb
#	lab2CA.runs/impl_1/vivado.jou
#	lab2CA.runs/impl_1/vivado.pb
#	lab2CA.runs/synth_1/CPU9bits.dcp
#	lab2CA.runs/synth_1/CPU9bits.vds
#	lab2CA.runs/synth_1/CPU9bits_tb.tcl
#	lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt
#	lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
#	lab2CA.runs/synth_1/gen_run.xml
#	lab2CA.runs/synth_1/vivado.jou
#	lab2CA.runs/synth_1/vivado.pb
#	lab2CA.sim/sim_1/behav/xsim/webtalk.jou
#	lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou
#	lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou
#	lab2CA.sim/sim_1/behav/xsim/xelab.pb
#	lab2CA.sim/sim_1/behav/xsim/xvlog.pb
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
This commit is contained in:
Johannes
2019-03-24 19:02:52 -04:00
parent be06f4e457 4354aebf8c
commit 65b951cf82
20 changed files with 788 additions and 584 deletions
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103
lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt
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@@ -1,13 +1,13 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sun Mar 24 18:38:37 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_tb_utilization_synth.rpt -pb CPU9bits_tb_utilization_synth.pb
| Design : CPU9bits_tb
| Date : Sun Mar 24 16:58:30 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
| Design : CPU9bits
| Device : 7k160tifbg484-2L
| Design State : Fully Placed
-----------------------------------------------------------------------------------------------------------------
| Design State : Synthesized
-----------------------------------------------------------------------------------------------------------
Utilization Design Information
@@ -15,15 +15,14 @@ Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
@@ -31,15 +30,16 @@ Table of Contents
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs | 0 | 0 | 101400 | 0.00 |
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
| Slice LUTs* | 578 | 0 | 101400 | 0.57 |
| LUT as Logic | 578 | 0 | 101400 | 0.57 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 0 | 0 | 202800 | 0.00 |
| Register as Flip Flop | 0 | 0 | 202800 | 0.00 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
| Slice Registers | 235 | 0 | 202800 | 0.12 |
| Register as Flip Flop | 81 | 0 | 202800 | 0.04 |
| Register as Latch | 154 | 0 | 202800 | 0.08 |
| F7 Muxes | 6 | 0 | 50700 | 0.01 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
@@ -55,34 +55,13 @@ Table of Contents
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 154 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 0 | Yes | Reset | - |
| 81 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------------------------------------+------+-------+-----------+-------+
| Slice | 0 | 0 | 25350 | 0.00 |
| SLICEL | 0 | 0 | | |
| SLICEM | 0 | 0 | | |
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 0 | 0 | 202800 | 0.00 |
| Register driven from within the Slice | 0 | | | |
| Register driven from outside the Slice | 0 | | | |
| Unique Control Sets | 0 | | 25350 | 0.00 |
+------------------------------------------+------+-------+-----------+-------+
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
3. Memory
2. Memory
---------
+----------------+------+-------+-----------+-------+
@@ -95,7 +74,7 @@ Table of Contents
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
3. DSP
------
+-----------+------+-------+-----------+-------+
@@ -105,13 +84,13 @@ Table of Contents
+-----------+------+-------+-----------+-------+
5. IO and GT Specific
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 0 | 0 | 285 | 0.00 |
| Bonded IOB | 3 | 0 | 285 | 1.05 |
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
@@ -132,13 +111,13 @@ Table of Contents
+-----------------------------+------+-------+-----------+-------+
6. Clocking
5. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
| BUFGCTRL | 2 | 0 | 32 | 6.25 |
| BUFIO | 0 | 0 | 32 | 0.00 |
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
@@ -148,7 +127,7 @@ Table of Contents
+------------+------+-------+-----------+-------+
7. Specific Feature
6. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
@@ -166,15 +145,27 @@ Table of Contents
+-------------+------+-------+-----------+-------+
8. Primitives
7. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT6 | 439 | LUT |
| LDCE | 154 | Flop & Latch |
| FDRE | 81 | Flop & Latch |
| LUT5 | 69 | LUT |
| LUT4 | 51 | LUT |
| LUT3 | 50 | LUT |
| LUT2 | 45 | LUT |
| MUXF7 | 6 | MuxFx |
| IBUF | 2 | IO |
| BUFG | 2 | Clock |
| OBUF | 1 | IO |
+----------+------+---------------------+
9. Black Boxes
8. Black Boxes
--------------
+----------+------+
@@ -182,8 +173,8 @@ Table of Contents
+----------+------+
10. Instantiated Netlists
-------------------------
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |