Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts: # Bank_behav1.wcfg # lab2CA.runs/.jobs/vrs_config_42.xml # lab2CA.runs/impl_1/CPU9bits_tb.tcl # lab2CA.runs/impl_1/gen_run.xml # lab2CA.runs/impl_1/htr.txt # lab2CA.runs/impl_1/init_design.pb # lab2CA.runs/impl_1/opt_design.pb # lab2CA.runs/impl_1/place_design.pb # lab2CA.runs/impl_1/vivado.jou # lab2CA.runs/impl_1/vivado.pb # lab2CA.runs/synth_1/CPU9bits.dcp # lab2CA.runs/synth_1/CPU9bits.vds # lab2CA.runs/synth_1/CPU9bits_tb.tcl # lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt # lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb # lab2CA.runs/synth_1/gen_run.xml # lab2CA.runs/synth_1/vivado.jou # lab2CA.runs/synth_1/vivado.pb # lab2CA.sim/sim_1/behav/xsim/webtalk.jou # lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou # lab2CA.sim/sim_1/behav/xsim/webtalk_15032.backup.jou # lab2CA.sim/sim_1/behav/xsim/xelab.pb # lab2CA.sim/sim_1/behav/xsim/xvlog.pb # lab2CA.srcs/sources_1/new/instructionMemory.v # lab2CA.xpr
This commit is contained in:
Johannes
@@ -79,120 +79,136 @@ module instructionMemory(
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// memory[39] <= 9'b000000000;
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// Bubble Sort
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// memory[0] <= 9'b000000001;
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// memory[1] <= 9'b010000000;
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// memory[2] <= 9'b000100000;
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// memory[3] <= 9'b010001000;
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// memory[4] <= 9'b010010000;
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// memory[5] <= 9'b010011000;
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// memory[6] <= 9'b101001000;
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// memory[7] <= 9'b101001010;
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// memory[8] <= 9'b100100011;
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// memory[9] <= 9'b101001001;
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// memory[10] <= 9'b011001001;
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// memory[11] <= 9'b101001000;
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// memory[12] <= 9'b101001001;
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// memory[13] <= 9'b011101000;
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// memory[14] <= 9'b110001010;
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// memory[15] <= 9'b100100001;
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// memory[16] <= 9'b100110100;
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// memory[17] <= 9'b101001001;
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// memory[18] <= 9'b011001001;
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// memory[19] <= 9'b000110010;
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// memory[20] <= 9'b011001001;
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// memory[21] <= 9'b000111010;
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// memory[22] <= 9'b101011110;
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// memory[23] <= 9'b011111100;
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// memory[24] <= 9'b110011010;
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// memory[25] <= 9'b100100001;
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// memory[26] <= 9'b101110010;
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// memory[27] <= 9'b101001001;
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// memory[28] <= 9'b011001001;
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// memory[29] <= 9'b101011111;
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// memory[30] <= 9'b001011010;
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// memory[31] <= 9'b011001001;
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// memory[32] <= 9'b001010010;
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// memory[33] <= 9'b010001000;
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// memory[34] <= 9'b011001001;
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// memory[35] <= 9'b101001010;
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// memory[36] <= 9'b101111100;
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// memory[37] <= 9'b101001011;
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// memory[38] <= 9'b110001001;
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// memory[39] <= 9'b100100001;
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// memory[40] <= 9'b100100011;
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// memory[41] <= 9'b010001000;
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// memory[42] <= 9'b101001000;
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// memory[43] <= 9'b101111011;
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// memory[44] <= 9'b000000000;
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// Bubble Sort
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memory[0] <= 9'b000000001; // nop
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// Setup
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memory[1] <= 9'b010000000; // zero $a
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memory[2] <= 9'b000100000; // lb $a, $a
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memory[3] <= 9'b010001000; // zero $b
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memory[4] <= 9'b010010000; // zero $c
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memory[5] <= 9'b010011000; // zero $d
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memory[6] <= 9'b101001000; // banks $b, $0
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memory[7] <= 9'b101001010; // banks $b, $1
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memory[8] <= 9'b100100011; // jf EndChk
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// Increment current index to compare next pair of values
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// Inc:
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memory[9] <= 9'b101001001; // bankl $b, $0
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memory[10] <= 9'b011001001; // addi $b, 1
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memory[11] <= 9'b101001000; // banks $b, $0
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// Check if at the end of the array
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// EndChk:
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memory[12] <= 9'b101001001; // bankl $b, $0
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memory[13] <= 9'b011101000; // slt $b, $a
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memory[14] <= 9'b110001010; // beq $b, JSC
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memory[15] <= 9'b100100001; // jf LoadNext
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// JSC:
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memory[16] <= 9'b100110100; // jf SwapChk
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// Load next values for comparison
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// LoadNext:
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memory[17] <= 9'b101001001; // bankl $b, $0
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memory[18] <= 9'b011001001; // addi $b, 1
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memory[19] <= 9'b000110010; // lb $c, $b
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memory[20] <= 9'b011001001; // addi $b, 1
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memory[21] <= 9'b000111010; // lb $d, $b
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// Compare loaded values to see if they need to be swapped
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memory[22] <= 9'b101011110; // banks $d, $3
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memory[23] <= 9'b011111100; // slt $d, $c
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memory[24] <= 9'b110011010; // beq $d, JI
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memory[25] <= 9'b100100001; // jf Swap
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// JI:
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memory[26] <= 9'b101110010; // jb Inc
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// Swap values in array
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// Swap:
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memory[27] <= 9'b101001001; // bankl $b, $0
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memory[28] <= 9'b011001001; // addi $b, 1
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memory[29] <= 9'b101011111; // bankl $d, $3
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memory[30] <= 9'b001011010; // sb $d, $b
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memory[31] <= 9'b011001001; // addi $b, 1
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memory[32] <= 9'b001010010; // sb $c, $b
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memory[33] <= 9'b010001000; // zero $b
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memory[34] <= 9'b011001001; // addi $b, 1
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memory[35] <= 9'b101001010; // banks $b, $1
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memory[36] <= 9'b101111100; // jb Inc
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// Check to see if any swaps have been made in the last iteration
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// SwapChk:
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memory[37] <= 9'b101001011; // bankl $b, $1
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memory[38] <= 9'b110001001; // beq $b, JE
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memory[39] <= 9'b100100001; // jf Reset
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// JE:
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memory[40] <= 9'b100100011; // jf End
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// Reset:
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memory[41] <= 9'b010001000; // zero $b
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memory[42] <= 9'b101001000; // banks $b, $0
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memory[43] <= 9'b101111011; // jb LoadNext
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// End:
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memory[44] <= 9'b000000000; // halt
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// Binary Search
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// memory[0] <= 9'b000000000;
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// memory[1] <= 9'b000000000;
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// memory[2] <= 9'b000000000;
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// memory[3] <= 9'b000000000;
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// memory[4] <= 9'b000000000;
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// memory[5] <= 9'b000000000;
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// memory[6] <= 9'b011001011; //addi R1, 3 (N = 3)
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// memory[7] <= 9'b011001011; //addi R1, 3 (N = 3)
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// memory[8] <= 9'b011001011; //addi R1, 3 (N = 3)
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// memory[9] <= 9'b011001011; //addi R1, 3 (N = 3)
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// memory[10] <= 9'b011001011; //addi R1, 3 (N = 3)
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// memory[11] <= 9'b011010010; //addi R2, 2 (inputAddr = 2)
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// memory[12] <= 9'b000111110; //lb R3, R3
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// memory[13] <= 9'b101011010; //banks R3, 1
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// memory[14] <= 9'b011001011; //addi R1, 3 (N = 3)
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// memory[15] <= 9'b101000000; //loop: banks R0, 0
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// memory[16] <= 9'b011100010; //slt R0, R1
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// memory[17] <= 9'b110000001; //beq R0, Exit
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// memory[18] <= 9'b100100001; //j Skip0
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// memory[19] <= 9'b100101110; //Exit: j Loose
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// memory[20] <= 9'b010101000; //Skip0: add R2, R0
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// memory[21] <= 9'b010101010; //add R2, R1
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// memory[22] <= 9'b111110000; //sll R2
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// memory[23] <= 9'b101011011; //bankl R3,1
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// memory[24] <= 9'b010111100; //add R3, R2
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// memory[25] <= 9'b101001100; //banks R1, 2
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// memory[26] <= 9'b000100110; //lb R0, R3
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// memory[27] <= 9'b010001000; //zero R1
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// memory[28] <= 9'b011001010; //addi R1, 1 (numAddr = 1)
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// memory[29] <= 9'b000101010; //lb R1, R1
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// memory[30] <= 9'b100100001; //j SkipU
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// memory[31] <= 9'b101110001; //j TransLoop
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// memory[32] <= 9'b101010110; //SkipU: banks R2, 3
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// memory[33] <= 9'b100100001; //j SkipD
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// memory[34] <= 9'b100110111; //j TransLoose
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// memory[35] <= 9'b010010000; //SkipD: zero R2
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// memory[36] <= 9'b010110010; //add R2, R1
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// memory[37] <= 9'b010101001; //sub R1, R0
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// memory[38] <= 9'b110001001; //beq R1, Go1
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// memory[39] <= 9'b100100001; //j Skip1
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// memory[40] <= 9'b100101001; //Go1: j Win
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// memory[41] <= 9'b010001000; //Skip1: zero R1
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// memory[42] <= 9'b010101100; //add R1, R2
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// memory[43] <= 9'b011100010; //slt R0, R1
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// memory[44] <= 9'b110001001; //beq R1, Go2
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// memory[45] <= 9'b100100110; //j Skip2
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// memory[46] <= 9'b010000000; //Go2: zero R0
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// memory[47] <= 9'b011000010; //addi R0, 1
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// memory[48] <= 9'b101001111; //bankl R1,3
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// memory[49] <= 9'b010100010; //add R0, R1
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// memory[50] <= 9'b101001101; //bankl R1,2
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// memory[51] <= 9'b101110101; //j loop
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// memory[52] <= 9'b010001000; //Skip2: zero R1
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// memory[53] <= 9'b011001111; //addi R1, -1
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// memory[54] <= 9'b101000111; //bankl R0, 3
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// memory[55] <= 9'b010101000; //add R1, R0
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// memory[56] <= 9'b101000001; //bankl R0,0
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// memory[57] <= 9'b101111011; //j loop
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// memory[58] <= 9'b010000000; //Loose: zero R0
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// memory[59] <= 9'b011000111; //addi R0, -1
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// memory[60] <= 9'b101000110; //banks R0, 3
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// memory[61] <= 9'b100100000; //j Win
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// memory[62] <= 9'b000000000; //Win: halt
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memory[0] <= 9'b000000000;
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memory[1] <= 9'b000000000;
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memory[2] <= 9'b000000000;
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memory[3] <= 9'b000000000;
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memory[4] <= 9'b000000000;
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memory[5] <= 9'b011001011; //addi R1, 3 (N = 3)
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memory[6] <= 9'b011001011; //addi R1, 3 (N = 3)
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memory[7] <= 9'b011001011; //addi R1, 3 (N = 3)
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memory[8] <= 9'b011001011; //addi R1, 3 (N = 3)
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memory[9] <= 9'b011001011; //addi R1, 3 (N = 3)
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memory[10] <= 9'b011011010; //addi R3, 2 (inputAddr = 2)
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memory[11] <= 9'b000111110; //lb R3, R3
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memory[12] <= 9'b101011010; //banks R3, 1
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memory[13] <= 9'b011001011; //addi R1, 3 (N = 3)
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memory[14] <= 9'b101000000; //loop: banks R0, 0
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memory[15] <= 9'b011100010; //slt R0, R1
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memory[16] <= 9'b110000001; //beq R0, Exit
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memory[17] <= 9'b100100001; //j Skip0
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memory[18] <= 9'b100101111; //Exit: j Loose
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memory[19] <= 9'b101000001; //Skip0: bankl R0, 0
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memory[20] <= 9'b010110000; //add R2, R0
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memory[21] <= 9'b010110010; //add R2, R1
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memory[22] <= 9'b111110001; //srl R2
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memory[23] <= 9'b101011011; //bankl R3,1
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memory[24] <= 9'b010111100; //add R3, R2
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memory[25] <= 9'b101001100; //banks R1, 2
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memory[26] <= 9'b000100110; //lb R0, R3
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memory[27] <= 9'b010001000; //zero R1
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memory[28] <= 9'b011001001; //addi R1, 1 (numAddr = 1)
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memory[29] <= 9'b000101010; //lb R1, R1
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memory[30] <= 9'b100100001; //j SkipU
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memory[31] <= 9'b101110010; //j TransLoop
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memory[32] <= 9'b101010110; //SkipU: banks R2, 3
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memory[33] <= 9'b100100001; //j SkipD
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memory[34] <= 9'b100110111; //j TransLoose
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memory[35] <= 9'b010010000; //SkipD: zero R2
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memory[36] <= 9'b010110010; //add R2, R1
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memory[37] <= 9'b010101001; //sub R1, R0
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memory[38] <= 9'b110001001; //beq R1, Go1
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memory[39] <= 9'b100100001; //j Skip1
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memory[40] <= 9'b100101001; //Go1: j Win
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memory[41] <= 9'b010001000; //Skip1: zero R1
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memory[42] <= 9'b010101100; //add R1, R2
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memory[43] <= 9'b011100010; //slt R0, R1
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memory[44] <= 9'b110000001; //beq R0, Go2
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memory[45] <= 9'b100100110; //j Skip2
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memory[46] <= 9'b010000000; //Go2: zero R0
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memory[47] <= 9'b011000001; //addi R0, 1
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memory[48] <= 9'b101001111; //bankl R1,3
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memory[49] <= 9'b010100010; //add R0, R1
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memory[50] <= 9'b101001101; //bankl R1,2
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memory[51] <= 9'b101110101; //j loop
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memory[52] <= 9'b010001000; //Skip2: zero R1
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memory[53] <= 9'b011001111; //addi R1, -1
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memory[54] <= 9'b101000111; //bankl R0, 3
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memory[55] <= 9'b010101000; //add R1, R0
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memory[56] <= 9'b101000001; //bankl R0,0
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memory[57] <= 9'b101111011; //j loop
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memory[58] <= 9'b010000000; //Loose: zero R0
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memory[59] <= 9'b011000111; //addi R0, -1
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memory[60] <= 9'b101000110; //banks R0, 3
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memory[61] <= 9'b100100000; //j Win
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memory[62] <= 9'b000000000; //Win: halt
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end
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