Making fixes to Bubble Sort
This commit is contained in:
WilliamMiceli
173
lab2CA.runs/impl_1/CPU9bits_tb.vdi
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173
lab2CA.runs/impl_1/CPU9bits_tb.vdi
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#-----------------------------------------------------------
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# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Sun Mar 24 18:38:44 2019
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# Process ID: 13064
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# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
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# Command line: vivado.exe -log CPU9bits_tb.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits_tb.tcl -notrace
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# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb.vdi
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# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
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#-----------------------------------------------------------
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source CPU9bits_tb.tcl -notrace
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Command: link_design -top CPU9bits_tb -part xc7k160tifbg484-2L
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Design is defaulting to srcset: sources_1
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Design is defaulting to constrset: constrs_1
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INFO: [Project 1-479] Netlist was created with Vivado 2018.3
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INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 579.477 ; gain = 0.000
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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link_design completed successfully
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link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:16 . Memory (MB): peak = 579.477 ; gain = 327.758
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Command: opt_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
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Running DRC as a precondition to command opt_design
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Starting DRC Task
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Project 1-461] DRC finished with 0 Errors
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INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 583.891 ; gain = 4.082
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Starting Cache Timing Information Task
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Ending Cache Timing Information Task | Checksum: f67b9b0d
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Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1077.012 ; gain = 493.121
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Starting Logic Optimization Task
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Phase 1 Retarget
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Opt 31-49] Retargeted 0 cell(s).
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Phase 1 Retarget | Checksum: f67b9b0d
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1167.297 ; gain = 0.000
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INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
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Phase 2 Constant propagation
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Phase 2 Constant propagation | Checksum: f67b9b0d
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1167.297 ; gain = 0.000
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INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
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Phase 3 Sweep
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Phase 3 Sweep | Checksum: f67b9b0d
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1167.297 ; gain = 0.000
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INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
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Phase 4 BUFG optimization
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Phase 4 BUFG optimization | Checksum: f67b9b0d
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1167.297 ; gain = 0.000
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INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
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Phase 5 Shift Register Optimization
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Phase 5 Shift Register Optimization | Checksum: f67b9b0d
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1167.297 ; gain = 0.000
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INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
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Phase 6 Post Processing Netlist
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Phase 6 Post Processing Netlist | Checksum: f67b9b0d
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.060 . Memory (MB): peak = 1167.297 ; gain = 0.000
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INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
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Opt_design Change Summary
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=========================
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-------------------------------------------------------------------------------------------------------------------------
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| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
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-------------------------------------------------------------------------------------------------------------------------
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| Retarget | 0 | 0 | 0 |
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| Constant propagation | 0 | 0 | 0 |
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| Sweep | 0 | 0 | 0 |
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| BUFG optimization | 0 | 0 | 0 |
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| Shift Register Optimization | 0 | 0 | 0 |
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| Post Processing Netlist | 0 | 0 | 0 |
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-------------------------------------------------------------------------------------------------------------------------
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Starting Connectivity Check Task
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000
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Ending Logic Optimization Task | Checksum: f67b9b0d
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.062 . Memory (MB): peak = 1167.297 ; gain = 0.000
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Starting Power Optimization Task
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INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
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Ending Power Optimization Task | Checksum: f67b9b0d
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1167.297 ; gain = 0.000
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Starting Final Cleanup Task
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Ending Final Cleanup Task | Checksum: f67b9b0d
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000
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Starting Netlist Obfuscation Task
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000
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Ending Netlist Obfuscation Task | Checksum: f67b9b0d
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000
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INFO: [Common 17-83] Releasing license: Implementation
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20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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opt_design completed successfully
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opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1167.297 ; gain = 587.559
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000
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WARNING: [Constraints 18-5210] No constraints selected for write.
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Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
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INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx
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Command: report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt.
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report_drc completed successfully
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Command: place_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Running DRC as a precondition to command place_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Placer Task
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INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
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Phase 1 Placer Initialization
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Phase 1.1 Placer Initialization Netlist Sorting
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1192.641 ; gain = 0.000
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Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 00000000
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1192.641 ; gain = 0.328
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Phase 1 Placer Initialization | Checksum: 00000000
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1192.641 ; gain = 0.328
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ERROR: [Place 30-494] The design is empty
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Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports.
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Ending Placer Task | Checksum: 00000000
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1192.641 ; gain = 0.328
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INFO: [Common 17-83] Releasing license: Implementation
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36 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered.
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place_design failed
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ERROR: [Common 17-69] Command failed: Placer could not place all instances
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INFO: [Common 17-206] Exiting Vivado at Sun Mar 24 18:39:16 2019...
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BIN
lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.pb
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BIN
lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.pb
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Binary file not shown.
49
lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt
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lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt
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@@ -0,0 +1,49 @@
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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------------------------------------------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
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| Date : Sun Mar 24 18:39:15 2019
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| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
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| Command : report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx
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| Design : CPU9bits_tb
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| Device : xc7k160tifbg484-2L
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| Speed File : -2L
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| Design State : Fully Routed
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------------------------------------------------------------------------------------------------------------------------
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Report DRC
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Table of Contents
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-----------------
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1. REPORT SUMMARY
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2. REPORT DETAILS
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1. REPORT SUMMARY
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-----------------
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Netlist: netlist
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Floorplan: design_1
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Design limits: <entire design considered>
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Ruledeck: default
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Max violations: <unlimited>
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Violations found: 1
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+----------+----------+-----------------------------------------------------+------------+
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| Rule | Severity | Description | Violations |
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+----------+----------+-----------------------------------------------------+------------+
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| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
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+----------+----------+-----------------------------------------------------+------------+
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2. REPORT DETAILS
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-----------------
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CFGBVS-1#1 Warning
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Missing CFGBVS and CONFIG_VOLTAGE Design Properties
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Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
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set_property CFGBVS value1 [current_design]
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#where value1 is either VCCO or GND
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set_property CONFIG_VOLTAGE value2 [current_design]
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#where value2 is the voltage provided to configuration bank 0
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Refer to the device configuration user guide for more information.
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Related violations: <none>
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BIN
lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp
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BIN
lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp
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Binary file not shown.
BIN
lab2CA.runs/impl_1/init_design.pb
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BIN
lab2CA.runs/impl_1/init_design.pb
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Binary file not shown.
BIN
lab2CA.runs/impl_1/opt_design.pb
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BIN
lab2CA.runs/impl_1/opt_design.pb
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Binary file not shown.
BIN
lab2CA.runs/impl_1/place_design.pb
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BIN
lab2CA.runs/impl_1/place_design.pb
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Binary file not shown.
BIN
lab2CA.runs/impl_1/route_design.pb
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BIN
lab2CA.runs/impl_1/route_design.pb
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Binary file not shown.
12
lab2CA.runs/impl_1/vivado.jou
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lab2CA.runs/impl_1/vivado.jou
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#-----------------------------------------------------------
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# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Sun Mar 24 18:38:44 2019
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# Process ID: 13064
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# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
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# Command line: vivado.exe -log CPU9bits_tb.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits_tb.tcl -notrace
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# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb.vdi
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# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
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#-----------------------------------------------------------
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source CPU9bits_tb.tcl -notrace
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4
lab2CA.runs/impl_1/vivado.pb
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4
lab2CA.runs/impl_1/vivado.pb
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End Record
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