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Making fixes to Bubble Sort

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This commit is contained in:
WilliamMiceli
2019-03-24 19:26:14 -04:00
parent 4354aebf8c
commit 7490815502
37 changed files with 1887 additions and 353 deletions
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304
CPU9bits_tb_behav.wcfg
View File

@@ -11,15 +11,15 @@
</db_ref> </db_ref>
</db_ref_list> </db_ref_list>
<zoom_setting> <zoom_setting>
<ZoomStartTime time="2650000fs"></ZoomStartTime> <ZoomStartTime time="179098989fs"></ZoomStartTime>
<ZoomEndTime time="76750001fs"></ZoomEndTime> <ZoomEndTime time="282180203fs"></ZoomEndTime>
<Cursor1Time time="15000000fs"></Cursor1Time> <Cursor1Time time="265000000fs"></Cursor1Time>
</zoom_setting> </zoom_setting>
<column_width_setting> <column_width_setting>
<NameColumnWidth column_width="188"></NameColumnWidth> <NameColumnWidth column_width="188"></NameColumnWidth>
<ValueColumnWidth column_width="104"></ValueColumnWidth> <ValueColumnWidth column_width="96"></ValueColumnWidth>
</column_width_setting> </column_width_setting>
<WVObjectSize size="31" /> <WVObjectSize size="11" />
<wvobject fp_name="/CPU9bits_tb/clk" type="logic"> <wvobject fp_name="/CPU9bits_tb/clk" type="logic">
<obj_property name="ElementShortName">clk</obj_property> <obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property> <obj_property name="ObjectShortName">clk</obj_property>
@@ -35,133 +35,217 @@
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/instr" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/instr" type="array">
<obj_property name="ElementShortName">instr[8:0]</obj_property> <obj_property name="ElementShortName">instr[8:0]</obj_property>
<obj_property name="ObjectShortName">instr[8:0]</obj_property> <obj_property name="ObjectShortName">instr[8:0]</obj_property>
<obj_property name="isExpanded"></obj_property> <obj_property name="Radix">BINARYRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/AddrOut" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/AddrOut" type="array">
<obj_property name="ElementShortName">AddrOut[8:0]</obj_property> <obj_property name="ElementShortName">AddrOut[8:0]</obj_property>
<obj_property name="ObjectShortName">AddrOut[8:0]</obj_property> <obj_property name="ObjectShortName">AddrOut[8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r0_out" type="array"> <wvobject fp_name="group429" type="group">
<obj_property name="label">Registers</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r0_out[8:0]</obj_property> <obj_property name="isExpanded"></obj_property>
<obj_property name="ObjectShortName">r0_out[8:0]</obj_property> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r0_out" type="array">
<obj_property name="label">RegisterA</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r0_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r0_out[8:0]</obj_property>
<obj_property name="label">RegisterA</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r1_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r1_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r1_out[8:0]</obj_property>
<obj_property name="label">RegisterB</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r2_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r2_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r2_out[8:0]</obj_property>
<obj_property name="label">RegisterC</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r3_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r3_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r3_out[8:0]</obj_property>
<obj_property name="label">RegisterD</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r1_out" type="array"> <wvobject fp_name="group430" type="group">
<obj_property name="label">Banks</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r1_out[8:0]</obj_property> <obj_property name="isExpanded"></obj_property>
<obj_property name="ObjectShortName">r1_out[8:0]</obj_property> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/r0_out" type="array">
<obj_property name="label">RegisterB</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r0_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r0_out[8:0]</obj_property>
<obj_property name="label">Bank0</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/r1_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r1_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r1_out[8:0]</obj_property>
<obj_property name="label">Bank1</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/r2_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r2_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r2_out[8:0]</obj_property>
<obj_property name="label">Bank2</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/r3_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r3_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r3_out[8:0]</obj_property>
<obj_property name="label">Bank3</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r2_out" type="array"> <wvobject type="divider" fp_name="divider431">
<obj_property name="label">Divider</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r2_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r2_out[8:0]</obj_property>
<obj_property name="label">RegisterC</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r3_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r3_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r3_out[8:0]</obj_property>
<obj_property name="label">RegisterD</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/r0_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r0_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r0_out[8:0]</obj_property>
<obj_property name="label">Bank0</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/r1_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r1_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r1_out[8:0]</obj_property>
<obj_property name="label">Bank1</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/r2_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r2_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r2_out[8:0]</obj_property>
<obj_property name="label">Bank2</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/r3_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r3_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r3_out[8:0]</obj_property>
<obj_property name="label">Bank3</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/mux4/switch" type="logic">
<obj_property name="ElementShortName">switch</obj_property>
<obj_property name="ObjectShortName">switch</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/writeEnable" type="logic">
<obj_property name="ElementShortName">writeEnable</obj_property>
<obj_property name="ObjectShortName">writeEnable</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/address" type="array">
<obj_property name="ElementShortName">address[8:0]</obj_property>
<obj_property name="ObjectShortName">address[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/writeData" type="array">
<obj_property name="ElementShortName">writeData[8:0]</obj_property>
<obj_property name="ObjectShortName">writeData[8:0]</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory" type="array">
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">memory[15:0][8:0]</obj_property> <obj_property name="ElementShortName">memory[23:0][8:0]</obj_property>
<obj_property name="ObjectShortName">memory[15:0][8:0]</obj_property> <obj_property name="ObjectShortName">memory[23:0][8:0]</obj_property>
<obj_property name="label">Data Memory</obj_property> <obj_property name="label">Data Memory</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<obj_property name="isExpanded"></obj_property> <obj_property name="isExpanded"></obj_property>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[23]" type="array">
<obj_property name="ElementShortName">[23][8:0]</obj_property>
<obj_property name="ObjectShortName">[23][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[22]" type="array">
<obj_property name="ElementShortName">[22][8:0]</obj_property>
<obj_property name="ObjectShortName">[22][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[21]" type="array">
<obj_property name="ElementShortName">[21][8:0]</obj_property>
<obj_property name="ObjectShortName">[21][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[20]" type="array">
<obj_property name="ElementShortName">[20][8:0]</obj_property>
<obj_property name="ObjectShortName">[20][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[19]" type="array">
<obj_property name="ElementShortName">[19][8:0]</obj_property>
<obj_property name="ObjectShortName">[19][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[18]" type="array">
<obj_property name="ElementShortName">[18][8:0]</obj_property>
<obj_property name="ObjectShortName">[18][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[17]" type="array">
<obj_property name="ElementShortName">[17][8:0]</obj_property>
<obj_property name="ObjectShortName">[17][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[16]" type="array">
<obj_property name="ElementShortName">[16][8:0]</obj_property>
<obj_property name="ObjectShortName">[16][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[15]" type="array">
<obj_property name="ElementShortName">[15][8:0]</obj_property>
<obj_property name="ObjectShortName">[15][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[14]" type="array">
<obj_property name="ElementShortName">[14][8:0]</obj_property>
<obj_property name="ObjectShortName">[14][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[13]" type="array">
<obj_property name="ElementShortName">[13][8:0]</obj_property>
<obj_property name="ObjectShortName">[13][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[12]" type="array">
<obj_property name="ElementShortName">[12][8:0]</obj_property>
<obj_property name="ObjectShortName">[12][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[11]" type="array">
<obj_property name="ElementShortName">[11][8:0]</obj_property>
<obj_property name="ObjectShortName">[11][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[10]" type="array">
<obj_property name="ElementShortName">[10][8:0]</obj_property>
<obj_property name="ObjectShortName">[10][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[9]" type="array">
<obj_property name="ElementShortName">[9][8:0]</obj_property>
<obj_property name="ObjectShortName">[9][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[8]" type="array">
<obj_property name="ElementShortName">[8][8:0]</obj_property>
<obj_property name="ObjectShortName">[8][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[7]" type="array">
<obj_property name="ElementShortName">[7][8:0]</obj_property>
<obj_property name="ObjectShortName">[7][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[6]" type="array">
<obj_property name="ElementShortName">[6][8:0]</obj_property>
<obj_property name="ObjectShortName">[6][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[5]" type="array">
<obj_property name="ElementShortName">[5][8:0]</obj_property>
<obj_property name="ObjectShortName">[5][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[4]" type="array">
<obj_property name="ElementShortName">[4][8:0]</obj_property>
<obj_property name="ObjectShortName">[4][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[3]" type="array">
<obj_property name="ElementShortName">[3][8:0]</obj_property>
<obj_property name="ObjectShortName">[3][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[2]" type="array">
<obj_property name="ElementShortName">[2][8:0]</obj_property>
<obj_property name="ObjectShortName">[2][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[1]" type="array">
<obj_property name="ElementShortName">[1][8:0]</obj_property>
<obj_property name="ObjectShortName">[1][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[0]" type="array">
<obj_property name="ElementShortName">[0][8:0]</obj_property>
<obj_property name="ObjectShortName">[0][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/readData" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/readData" type="array">
<obj_property name="ElementShortName">readData[8:0]</obj_property> <obj_property name="ElementShortName">readData[8:0]</obj_property>
<obj_property name="ObjectShortName">readData[8:0]</obj_property> <obj_property name="ObjectShortName">readData[8:0]</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/operand0" type="array">
<obj_property name="ElementShortName">operand0[8:0]</obj_property>
<obj_property name="ObjectShortName">operand0[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_K" type="array">
<obj_property name="ElementShortName">result_K[8:0]</obj_property>
<obj_property name="ObjectShortName">result_K[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/op_idx" type="logic">
<obj_property name="ElementShortName">op_idx</obj_property>
<obj_property name="ObjectShortName">op_idx</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/AddrIn" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/AddrIn" type="array">
<obj_property name="ElementShortName">AddrIn[8:0]</obj_property> <obj_property name="ElementShortName">AddrIn[8:0]</obj_property>
<obj_property name="ObjectShortName">AddrIn[8:0]</obj_property> <obj_property name="ObjectShortName">AddrIn[8:0]</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/progC_out" type="array">
<obj_property name="ElementShortName">progC_out[8:0]</obj_property>
<obj_property name="ObjectShortName">progC_out[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/result_m" type="array">
<obj_property name="ElementShortName">result_m[8:0]</obj_property>
<obj_property name="ObjectShortName">result_m[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/cout" type="logic">
<obj_property name="ElementShortName">cout</obj_property>
<obj_property name="ObjectShortName">cout</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result" type="array">
<obj_property name="ElementShortName">result[8:0]</obj_property>
<obj_property name="ObjectShortName">result[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/mux0/switch" type="array">
<obj_property name="ElementShortName">switch[3:0]</obj_property>
<obj_property name="ObjectShortName">switch[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/mux0/K" type="array">
<obj_property name="ElementShortName">K[8:0]</obj_property>
<obj_property name="ObjectShortName">K[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/mux0/out" type="array">
<obj_property name="ElementShortName">out[8:0]</obj_property>
<obj_property name="ObjectShortName">out[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/CU/FU" type="array">
<obj_property name="ElementShortName">FU[2:0]</obj_property>
<obj_property name="ObjectShortName">FU[2:0]</obj_property>
</wvobject>
</wave_config> </wave_config>

124
lab2CA.cache/wt/webtalk_pa.xml
View File

@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Sun Mar 24 17:04:55 2019"> <application name="pa" timeStamp="Sun Mar 24 19:27:42 2019">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="88e779ed22f94d2db93b335d17c75f15" type="ProjectID"/> <property name="ProjectID" value="88e779ed22f94d2db93b335d17c75f15" type="ProjectID"/>
<property name="ProjectIteration" value="19" type="ProjectIteration"/> <property name="ProjectIteration" value="21" type="ProjectIteration"/>
</section> </section>
<section name="PlanAhead Usage" visible="true"> <section name="PlanAhead Usage" visible="true">
<item name="Project Data"> <item name="Project Data">
@@ -17,7 +17,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/> <property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item> </item>
<item name="Java Command Handlers"> <item name="Java Command Handlers">
<property name="CloseProject" value="16" type="JavaHandler"/> <property name="CloseProject" value="17" type="JavaHandler"/>
<property name="EditDelete" value="2" type="JavaHandler"/> <property name="EditDelete" value="2" type="JavaHandler"/>
<property name="FlipToViewTaskRTLAnalysis" value="1" type="JavaHandler"/> <property name="FlipToViewTaskRTLAnalysis" value="1" type="JavaHandler"/>
<property name="OpenDesign" value="1" type="JavaHandler"/> <property name="OpenDesign" value="1" type="JavaHandler"/>
@@ -25,49 +25,52 @@ This means code written to parse this file will need to be revisited each subseq
<property name="OpenProject" value="3" type="JavaHandler"/> <property name="OpenProject" value="3" type="JavaHandler"/>
<property name="ReloadDesign" value="1" type="JavaHandler"/> <property name="ReloadDesign" value="1" type="JavaHandler"/>
<property name="ReportTimingSummary" value="9" type="JavaHandler"/> <property name="ReportTimingSummary" value="9" type="JavaHandler"/>
<property name="RunImplementation" value="24" type="JavaHandler"/> <property name="RunImplementation" value="26" type="JavaHandler"/>
<property name="RunSchematic" value="22" type="JavaHandler"/> <property name="RunSchematic" value="27" type="JavaHandler"/>
<property name="RunSynthesis" value="19" type="JavaHandler"/> <property name="RunSynthesis" value="20" type="JavaHandler"/>
<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/> <property name="SaveFileProxyHandler" value="2" type="JavaHandler"/>
<property name="SaveLayoutAs" value="1" type="JavaHandler"/>
<property name="SetSourceEnabled" value="2" type="JavaHandler"/> <property name="SetSourceEnabled" value="2" type="JavaHandler"/>
<property name="SetTopNode" value="27" type="JavaHandler"/> <property name="SetTopNode" value="38" type="JavaHandler"/>
<property name="ShowSimulationDefaultWaveFormView" value="1" type="JavaHandler"/> <property name="ShowSimulationDefaultWaveFormView" value="1" type="JavaHandler"/>
<property name="ShowView" value="12" type="JavaHandler"/> <property name="ShowView" value="13" type="JavaHandler"/>
<property name="SimulationClose" value="5" type="JavaHandler"/> <property name="SimulationClose" value="6" type="JavaHandler"/>
<property name="SimulationRelaunch" value="61" type="JavaHandler"/> <property name="SimulationRelaunch" value="89" type="JavaHandler"/>
<property name="SimulationRun" value="89" type="JavaHandler"/> <property name="SimulationRun" value="94" type="JavaHandler"/>
<property name="TclFind" value="4" type="JavaHandler"/> <property name="TclFind" value="6" type="JavaHandler"/>
<property name="ToggleSelectAreaMode" value="2" type="JavaHandler"/> <property name="ToggleSelectAreaMode" value="2" type="JavaHandler"/>
<property name="ToggleViewNavigator" value="1" type="JavaHandler"/> <property name="ToggleViewNavigator" value="1" type="JavaHandler"/>
<property name="ToolsSettings" value="1" type="JavaHandler"/> <property name="ToolsSettings" value="2" type="JavaHandler"/>
<property name="UpdateSourceFiles" value="1" type="JavaHandler"/> <property name="UpdateSourceFiles" value="1" type="JavaHandler"/>
<property name="ViewLayoutCmd" value="1" type="JavaHandler"/> <property name="ViewLayoutCmd" value="2" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="2" type="JavaHandler"/> <property name="ViewTaskImplementation" value="2" type="JavaHandler"/>
<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/> <property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
<property name="ViewTaskRTLAnalysis" value="9" type="JavaHandler"/> <property name="ViewTaskRTLAnalysis" value="13" type="JavaHandler"/>
<property name="WaveformOpenConfiguration" value="1" type="JavaHandler"/> <property name="WaveformOpenConfiguration" value="1" type="JavaHandler"/>
<property name="WaveformSaveConfiguration" value="5" type="JavaHandler"/> <property name="WaveformSaveConfiguration" value="9" type="JavaHandler"/>
<property name="WaveformSaveConfigurationAs" value="1" type="JavaHandler"/> <property name="WaveformSaveConfigurationAs" value="1" type="JavaHandler"/>
<property name="ZoomFit" value="10" type="JavaHandler"/> <property name="ZoomFit" value="10" type="JavaHandler"/>
<property name="ZoomOut" value="1" type="JavaHandler"/> <property name="ZoomOut" value="3" type="JavaHandler"/>
</item> </item>
<item name="Gui Handlers"> <item name="Gui Handlers">
<property name="AbstractSaveAsDialog_NAME" value="2" type="GuiHandlerData"/>
<property name="AbstractSearchablePanel_SHOW_SEARCH" value="2" type="GuiHandlerData"/> <property name="AbstractSearchablePanel_SHOW_SEARCH" value="2" type="GuiHandlerData"/>
<property name="BaseDialogUtils_OPEN_IN_SPECIFIED_LAYOUT" value="1" type="GuiHandlerData"/> <property name="BaseDialogUtils_OPEN_IN_SPECIFIED_LAYOUT" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_APPLY" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="31" type="GuiHandlerData"/> <property name="BaseDialog_CANCEL" value="31" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="122" type="GuiHandlerData"/> <property name="BaseDialog_OK" value="131" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="19" type="GuiHandlerData"/> <property name="BaseDialog_YES" value="20" type="GuiHandlerData"/>
<property name="ClosePlanner_YES" value="1" type="GuiHandlerData"/> <property name="ClosePlanner_YES" value="1" type="GuiHandlerData"/>
<property name="CmdMsgDialog_MESSAGES" value="2" type="GuiHandlerData"/> <property name="CmdMsgDialog_MESSAGES" value="2" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="13" type="GuiHandlerData"/> <property name="CmdMsgDialog_OK" value="13" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="2" type="GuiHandlerData"/> <property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="2" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="370" type="GuiHandlerData"/> <property name="FileSetPanel_FILE_SET_PANEL_TREE" value="421" type="GuiHandlerData"/>
<property name="FloatingTopDialog_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="12" type="GuiHandlerData"/> <property name="FloatingTopDialog_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="12" type="GuiHandlerData"/>
<property name="FloatingTopDialog_SPECIFY_NEW_TOP_MODULE" value="10" type="GuiHandlerData"/> <property name="FloatingTopDialog_SPECIFY_NEW_TOP_MODULE" value="10" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="227" type="GuiHandlerData"/> <property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="254" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/> <property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="64" type="GuiHandlerData"/> <property name="GraphicalView_ZOOM_FIT" value="67" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="46" type="GuiHandlerData"/> <property name="GraphicalView_ZOOM_IN" value="47" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="35" type="GuiHandlerData"/> <property name="GraphicalView_ZOOM_OUT" value="35" type="GuiHandlerData"/>
<property name="HCodeEditor_BLANK_OPERATIONS" value="6" type="GuiHandlerData"/> <property name="HCodeEditor_BLANK_OPERATIONS" value="6" type="GuiHandlerData"/>
<property name="HCodeEditor_CLOSE" value="9" type="GuiHandlerData"/> <property name="HCodeEditor_CLOSE" value="9" type="GuiHandlerData"/>
@@ -77,104 +80,115 @@ This means code written to parse this file will need to be revisited each subseq
<property name="HInputHandler_INDENT_SELECTION" value="1" type="GuiHandlerData"/> <property name="HInputHandler_INDENT_SELECTION" value="1" type="GuiHandlerData"/>
<property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="15" type="GuiHandlerData"/> <property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="15" type="GuiHandlerData"/>
<property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/> <property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
<property name="InstanceMenu_FLOORPLANNING" value="1" type="GuiHandlerData"/>
<property name="LaunchPanel_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/> <property name="LaunchPanel_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_CHECKPOINT" value="6" type="GuiHandlerData"/> <property name="MainMenuMgr_CHECKPOINT" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_CONSTRAINTS" value="2" type="GuiHandlerData"/> <property name="MainMenuMgr_CONSTRAINTS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="10" type="GuiHandlerData"/> <property name="MainMenuMgr_EDIT" value="10" type="GuiHandlerData"/>
<property name="MainMenuMgr_EXPORT" value="5" type="GuiHandlerData"/> <property name="MainMenuMgr_EXPORT" value="5" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="50" type="GuiHandlerData"/> <property name="MainMenuMgr_FILE" value="54" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOW" value="8" type="GuiHandlerData"/> <property name="MainMenuMgr_FLOW" value="8" type="GuiHandlerData"/>
<property name="MainMenuMgr_IP" value="6" type="GuiHandlerData"/> <property name="MainMenuMgr_IP" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_BLOCK_DESIGN" value="2" type="GuiHandlerData"/> <property name="MainMenuMgr_OPEN_BLOCK_DESIGN" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="2" type="GuiHandlerData"/> <property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="26" type="GuiHandlerData"/> <property name="MainMenuMgr_PROJECT" value="28" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="4" type="GuiHandlerData"/> <property name="MainMenuMgr_REPORTS" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_RUN" value="2" type="GuiHandlerData"/> <property name="MainMenuMgr_RUN" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_SETTINGS" value="2" type="GuiHandlerData"/> <property name="MainMenuMgr_SETTINGS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_SIMULATION_WAVEFORM" value="12" type="GuiHandlerData"/> <property name="MainMenuMgr_SIMULATION_WAVEFORM" value="13" type="GuiHandlerData"/>
<property name="MainMenuMgr_TEXT_EDITOR" value="7" type="GuiHandlerData"/> <property name="MainMenuMgr_TEXT_EDITOR" value="7" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="6" type="GuiHandlerData"/> <property name="MainMenuMgr_TOOLS" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_VIEW" value="2" type="GuiHandlerData"/> <property name="MainMenuMgr_VIEW" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="8" type="GuiHandlerData"/> <property name="MainMenuMgr_WINDOW" value="8" type="GuiHandlerData"/>
<property name="MainToolbarMgr_RUN" value="2" type="GuiHandlerData"/> <property name="MainToolbarMgr_RUN" value="2" type="GuiHandlerData"/>
<property name="MainWinMenuMgr_LAYOUT" value="4" type="GuiHandlerData"/> <property name="MainWinMenuMgr_LAYOUT" value="4" type="GuiHandlerData"/>
<property name="MainWinToolbarMgr_SELECT_OR_SAVE_WINDOW_LAYOUT" value="1" type="GuiHandlerData"/> <property name="MainWinToolbarMgr_SELECT_OR_SAVE_WINDOW_LAYOUT" value="3" type="GuiHandlerData"/>
<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="4" type="GuiHandlerData"/> <property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="4" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_SEVERITY" value="2" type="GuiHandlerData"/> <property name="MsgTreePanel_MESSAGE_SEVERITY" value="2" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="126" type="GuiHandlerData"/> <property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="131" type="GuiHandlerData"/>
<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="5" type="GuiHandlerData"/> <property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="5" type="GuiHandlerData"/>
<property name="MsgView_WARNING_MESSAGES" value="3" type="GuiHandlerData"/> <property name="MsgView_WARNING_MESSAGES" value="3" type="GuiHandlerData"/>
<property name="NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE" value="116" type="GuiHandlerData"/> <property name="NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE" value="116" type="GuiHandlerData"/>
<property name="NetlistSchMenuAndMouse_EXPAND_COLLAPSE" value="1" type="GuiHandlerData"/> <property name="NetlistSchMenuAndMouse_EXPAND_COLLAPSE" value="1" type="GuiHandlerData"/>
<property name="NetlistSchMenuAndMouse_VIEW" value="2" type="GuiHandlerData"/> <property name="NetlistSchMenuAndMouse_VIEW" value="2" type="GuiHandlerData"/>
<property name="NetlistTreeView_NETLIST_TREE" value="1" type="GuiHandlerData"/> <property name="NetlistSchematicView_SHOW_IO_PORTS_IN_THIS_SCHEMATIC" value="1" type="GuiHandlerData"/>
<property name="NetlistTreeView_NETLIST_TREE" value="4" type="GuiHandlerData"/>
<property name="OpenFileAction_CANCEL" value="2" type="GuiHandlerData"/> <property name="OpenFileAction_CANCEL" value="2" type="GuiHandlerData"/>
<property name="OpenFileAction_OK" value="1" type="GuiHandlerData"/> <property name="OpenFileAction_OK" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="30" type="GuiHandlerData"/> <property name="PACommandNames_AUTO_UPDATE_HIER" value="42" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="15" type="GuiHandlerData"/> <property name="PACommandNames_CLOSE_PROJECT" value="16" type="GuiHandlerData"/>
<property name="PACommandNames_MESSAGE_WINDOW" value="1" type="GuiHandlerData"/> <property name="PACommandNames_MESSAGE_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/> <property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_RTL_DESIGN" value="1" type="GuiHandlerData"/> <property name="PACommandNames_OPEN_RTL_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RELOAD_RTL_DESIGN" value="1" type="GuiHandlerData"/> <property name="PACommandNames_RELOAD_RTL_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SCHEMATIC" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SELECT_AREA" value="2" type="GuiHandlerData"/> <property name="PACommandNames_SELECT_AREA" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_SET_AS_TOP" value="28" type="GuiHandlerData"/> <property name="PACommandNames_SET_AS_TOP" value="39" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_CLOSE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_DEFAULT_WAVEFORM_WINDOW" value="1" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_DEFAULT_WAVEFORM_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RELAUNCH" value="66" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_RELAUNCH" value="96" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN" value="3" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_RUN" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="88" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="93" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_FUNCTIONAL" value="1" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_FUNCTIONAL" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_TIMING" value="4" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_TIMING" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_SETTINGS" value="1" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_SETTINGS" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_ENABLE" value="1" type="GuiHandlerData"/> <property name="PACommandNames_SRC_ENABLE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_REPLACE_FILE" value="1" type="GuiHandlerData"/> <property name="PACommandNames_SRC_REPLACE_FILE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_TOGGLE_VIEW_NAV" value="1" type="GuiHandlerData"/> <property name="PACommandNames_TOGGLE_VIEW_NAV" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_FIT" value="10" type="GuiHandlerData"/> <property name="PACommandNames_ZOOM_FIT" value="10" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_OUT" value="1" type="GuiHandlerData"/> <property name="PACommandNames_ZOOM_OUT" value="3" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="32" type="GuiHandlerData"/> <property name="PAViews_CODE" value="34" type="GuiHandlerData"/>
<property name="PAViews_DEVICE" value="1" type="GuiHandlerData"/> <property name="PAViews_DEVICE" value="1" type="GuiHandlerData"/>
<property name="PAViews_PATH_TABLE" value="1" type="GuiHandlerData"/> <property name="PAViews_PATH_TABLE" value="1" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="60" type="GuiHandlerData"/> <property name="PAViews_PROJECT_SUMMARY" value="64" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="16" type="GuiHandlerData"/> <property name="PAViews_SCHEMATIC" value="23" type="GuiHandlerData"/>
<property name="PathReportTableView_DESCRIPTION" value="2" type="GuiHandlerData"/> <property name="PathReportTableView_DESCRIPTION" value="2" type="GuiHandlerData"/>
<property name="PlanAheadTab_SHOW_FLOW_NAVIGATOR" value="2" type="GuiHandlerData"/> <property name="PlanAheadTab_SHOW_FLOW_NAVIGATOR" value="2" type="GuiHandlerData"/>
<property name="PowerResultTab_REPORT_NAVIGATION_TREE" value="1" type="GuiHandlerData"/> <property name="PowerResultTab_REPORT_NAVIGATION_TREE" value="1" type="GuiHandlerData"/>
<property name="ProgressDialog_BACKGROUND" value="5" type="GuiHandlerData"/> <property name="PrimitivesMenu_HIGHLIGHT_LEAF_CELLS" value="1" type="GuiHandlerData"/>
<property name="ProgressDialog_BACKGROUND" value="7" type="GuiHandlerData"/>
<property name="ProgressDialog_CANCEL" value="5" type="GuiHandlerData"/> <property name="ProgressDialog_CANCEL" value="5" type="GuiHandlerData"/>
<property name="ProjectTab_RELOAD" value="17" type="GuiHandlerData"/> <property name="ProjectSettingsSimulationPanel_TABBED_PANE" value="2" type="GuiHandlerData"/>
<property name="ProjectTab_RELOAD" value="23" type="GuiHandlerData"/>
<property name="RDICommands_COPY" value="2" type="GuiHandlerData"/> <property name="RDICommands_COPY" value="2" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/> <property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
<property name="RDICommands_REDO" value="1" type="GuiHandlerData"/> <property name="RDICommands_REDO" value="1" type="GuiHandlerData"/>
<property name="RDICommands_SAVE_FILE" value="99" type="GuiHandlerData"/> <property name="RDICommands_SAVE_FILE" value="120" type="GuiHandlerData"/>
<property name="RDICommands_WAVEFORM_OPEN_CONFIGURATION" value="1" type="GuiHandlerData"/> <property name="RDICommands_WAVEFORM_OPEN_CONFIGURATION" value="1" type="GuiHandlerData"/>
<property name="RDICommands_WAVEFORM_SAVE_CONFIGURATION" value="3" type="GuiHandlerData"/> <property name="RDICommands_WAVEFORM_SAVE_CONFIGURATION" value="5" type="GuiHandlerData"/>
<property name="RDICommands_WAVEFORM_SAVE_CONFIGURATION_AS" value="1" type="GuiHandlerData"/> <property name="RDICommands_WAVEFORM_SAVE_CONFIGURATION_AS" value="1" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="756" type="GuiHandlerData"/> <property name="RDIViews_WAVEFORM_VIEWER" value="873" type="GuiHandlerData"/>
<property name="ReportTimingSummaryDialog_REPORT_TIMING_SUMMARY_DIALOG_TABBED" value="14" type="GuiHandlerData"/> <property name="ReportTimingSummaryDialog_REPORT_TIMING_SUMMARY_DIALOG_TABBED" value="14" type="GuiHandlerData"/>
<property name="ReportTimingSummaryDialog_REPORT_UNCONSTRAINED_PATHS" value="6" type="GuiHandlerData"/> <property name="ReportTimingSummaryDialog_REPORT_UNCONSTRAINED_PATHS" value="6" type="GuiHandlerData"/>
<property name="RunGadget_SHOW_ERROR" value="1" type="GuiHandlerData"/> <property name="RunGadget_SHOW_ERROR" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/> <property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="11" type="GuiHandlerData"/> <property name="SaveProjectUtils_SAVE" value="12" type="GuiHandlerData"/>
<property name="SelectMenu_HIGHLIGHT" value="1" type="GuiHandlerData"/>
<property name="SelectMenu_MARK" value="1" type="GuiHandlerData"/>
<property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="12" type="GuiHandlerData"/> <property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="12" type="GuiHandlerData"/>
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="61" type="GuiHandlerData"/> <property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="80" type="GuiHandlerData"/>
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="133" type="GuiHandlerData"/> <property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="139" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="31" type="GuiHandlerData"/> <property name="SrcMenu_IP_HIERARCHY" value="42" type="GuiHandlerData"/>
<property name="StaleMoreAction_OUT_OF_DATE_DETAILS" value="1" type="GuiHandlerData"/> <property name="StaleMoreAction_OUT_OF_DATE_DETAILS" value="1" type="GuiHandlerData"/>
<property name="StaleRunDialog_NO" value="3" type="GuiHandlerData"/> <property name="StaleRunDialog_NO" value="3" type="GuiHandlerData"/>
<property name="StaleRunDialog_YES" value="1" type="GuiHandlerData"/> <property name="StaleRunDialog_YES" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="23" type="GuiHandlerData"/> <property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="25" type="GuiHandlerData"/>
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/> <property name="SyntheticaStateMonitor_CANCEL" value="2" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="32" type="GuiHandlerData"/> <property name="TaskBanner_CLOSE" value="37" type="GuiHandlerData"/>
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/> <property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/>
<property name="TclFindDialog_RESULT_NAME" value="2" type="GuiHandlerData"/> <property name="TclFindDialog_RESULT_NAME" value="2" type="GuiHandlerData"/>
<property name="TimingDialogUtils_RESULTS_NAME" value="1" type="GuiHandlerData"/> <property name="TimingDialogUtils_RESULTS_NAME" value="1" type="GuiHandlerData"/>
<property name="TimingItemFlatTablePanel_TABLE" value="3" type="GuiHandlerData"/> <property name="TimingItemFlatTablePanel_TABLE" value="3" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="390" type="GuiHandlerData"/> <property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="478" type="GuiHandlerData"/>
<property name="WaveformView_GOTO_CURSOR" value="3" type="GuiHandlerData"/>
<property name="WaveformView_GOTO_LAST_TIME" value="1" type="GuiHandlerData"/>
<property name="WaveformView_GOTO_TIME_0" value="8" type="GuiHandlerData"/>
<property name="WaveformView_PREVIOUS_MARKER" value="1" type="GuiHandlerData"/> <property name="WaveformView_PREVIOUS_MARKER" value="1" type="GuiHandlerData"/>
</item> </item>
<item name="Other"> <item name="Other">
<property name="GuiMode" value="18" type="GuiMode"/> <property name="GuiMode" value="66" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/> <property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="16" type="TclMode"/> <property name="TclMode" value="65" type="TclMode"/>
</item> </item>
</section> </section>
</application> </application>

8
lab2CA.runs/.jobs/vrs_config_43.xml Normal file
View File

@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_44.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sun Mar 24 18:38:44 2019
# Process ID: 13064
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits_tb.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits_tb.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb.vdi
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits_tb.tcl -notrace
Command: link_design -top CPU9bits_tb -part xc7k160tifbg484-2L
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Project 1-570] Preparing netlist for logic optimization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 579.477 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:16 . Memory (MB): peak = 579.477 ; gain = 327.758
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 583.891 ; gain = 4.082
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: f67b9b0d
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1077.012 ; gain = 493.121
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: f67b9b0d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1167.297 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: f67b9b0d
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1167.297 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: f67b9b0d
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1167.297 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: f67b9b0d
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1167.297 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: f67b9b0d
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1167.297 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: f67b9b0d
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.060 . Memory (MB): peak = 1167.297 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 0 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000
Ending Logic Optimization Task | Checksum: f67b9b0d
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.062 . Memory (MB): peak = 1167.297 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: f67b9b0d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1167.297 ; gain = 0.000
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: f67b9b0d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: f67b9b0d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1167.297 ; gain = 587.559
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx
Command: report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1192.641 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 00000000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1192.641 ; gain = 0.328
Phase 1 Placer Initialization | Checksum: 00000000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1192.641 ; gain = 0.328
ERROR: [Place 30-494] The design is empty
Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports.
Ending Placer Task | Checksum: 00000000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1192.641 ; gain = 0.328
INFO: [Common 17-83] Releasing license: Implementation
36 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered.
place_design failed
ERROR: [Common 17-69] Command failed: Placer could not place all instances
INFO: [Common 17-206] Exiting Vivado at Sun Mar 24 18:39:16 2019...

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sun Mar 24 18:39:15 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx
| Design : CPU9bits_tb
| Device : xc7k160tifbg484-2L
| Speed File : -2L
| Design State : Fully Routed
------------------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 1
+----------+----------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+----------+-----------------------------------------------------+------------+
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
+----------+----------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>

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#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sun Mar 24 18:38:44 2019
# Process ID: 13064
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits_tb.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits_tb.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb.vdi
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits_tb.tcl -notrace

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End Record

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#
# Synthesis run script generated by Vivado
#
set TIME_start [clock seconds]
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
set_param synth.incrementalSynthesisCache C:/Users/willi/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-18452-WM-G75VW/incrSyn
set_msg_config -id {Synth 8-256} -limit 10000
set_msg_config -id {Synth 8-638} -limit 10000
create_project -in_memory -part xc7k160tifbg484-2L
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/wt} [current_project]
set_property parent.project_path {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr} [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo {c:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/ip} [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_verilog -library xil_defaultlib {
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v}
{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v}
}
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
set_param ips.enableIPCacheLiteLoad 1
close [open __synthesis_is_running__ w]
synth_design -top CPU9bits -part xc7k160tifbg484-2L
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef CPU9bits.dcp
create_report "synth_1_synth_report_utilization_0" "report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb"
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]

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#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sun Mar 24 18:28:31 2019
# Process ID: 5228
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log CPU9bits_tb.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.vds
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits_tb.tcl -notrace
Command: synth_design -top CPU9bits_tb -part xc7k160tifbg484-2L
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 14244
WARNING: [Synth 8-1958] event expressions must result in a singular type [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:85]
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 372.199 ; gain = 114.445
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'CPU9bits_tb' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:172]
WARNING: [Synth 8-85] always block has no event control specified [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:179]
INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
WARNING: [Synth 8-567] referenced signal 'writeEnable' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:85]
WARNING: [Synth 8-567] referenced signal 'writeData' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:85]
INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412]
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342]
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541]
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:17]
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356]
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (27#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits_tb' (28#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:172]
WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0]
WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0]
WARNING: [Synth 8-3331] design shift_left has unconnected port A[8]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:01:51 ; elapsed = 00:01:54 . Memory (MB): peak = 2338.125 ; gain = 2080.371
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:02:04 ; elapsed = 00:02:09 . Memory (MB): peak = 2338.125 ; gain = 2080.371
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k160tifbg484-2L
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:02:04 ; elapsed = 00:02:09 . Memory (MB): peak = 2338.125 ; gain = 2080.371
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "memory_reg[511]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[510]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[509]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[508]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[507]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[506]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[505]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[504]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[503]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[502]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[501]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[500]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[499]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[498]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[497]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[496]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[495]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[494]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[493]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[492]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[491]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[490]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[489]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[488]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[487]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[486]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[485]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[484]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[483]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[482]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[481]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[480]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[479]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[478]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[477]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[476]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[475]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[474]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[473]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[472]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[471]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[470]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[469]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[468]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[467]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[466]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[465]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[464]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[463]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[462]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[461]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[460]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[459]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[458]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[457]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[456]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[455]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[454]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[453]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[452]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[451]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[450]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[449]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[448]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[447]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[446]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[445]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[444]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[443]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[442]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[441]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[440]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[439]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[438]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[437]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[436]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[435]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[434]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[433]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[432]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[431]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[430]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[429]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[428]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[427]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[426]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[425]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[424]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[423]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[422]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[421]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[420]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[419]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[418]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[417]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[416]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[415]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[414]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[413]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "memory_reg[412]" won't be mapped to RAM because it is too sparse
INFO: [Common 17-14] Message 'Synth 8-5546' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:202]
WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[511]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[510]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[509]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[508]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[507]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[506]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[505]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[504]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[503]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[502]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[501]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[500]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[499]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[498]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[497]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[496]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[495]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[494]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[493]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[492]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[491]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[490]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[489]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[488]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[487]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[486]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[485]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[484]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[483]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[482]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[481]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[480]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[479]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[478]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[477]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[476]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[475]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[474]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[473]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[472]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[471]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[470]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[469]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[468]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[467]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[466]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[465]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[464]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[463]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[462]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[461]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[460]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[459]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[458]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[457]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[456]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[455]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[454]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[453]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[452]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[451]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[450]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[449]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[448]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[447]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[446]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[445]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[444]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[443]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[442]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[441]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[440]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[439]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[438]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[437]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[436]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[435]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[434]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[433]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[432]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[431]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[430]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[429]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[428]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[427]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[426]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[425]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[424]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[423]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[422]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[421]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[420]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[419]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[418]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[417]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[416]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[415]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[414]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:87]
INFO: [Common 17-14] Message 'Synth 8-327' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:04:25 ; elapsed = 00:04:33 . Memory (MB): peak = 2906.012 ; gain = 2648.258
---------------------------------------------------------------------------------
INFO: [Synth 8-223] decloning instance 'CPU9bits0/SE1' (sign_extend_3bit) to 'CPU9bits0/SE3'
Report RTL Partitions:
+------+----------------+------------+----------+
| |RTL Partition |Replication |Instances |
+------+----------------+------------+----------+
|1 |dataMemory__GB0 | 1| 2378380|
|2 |CPU9bits__GC0 | 1| 1169|
+------+----------------+------------+----------+
No constraint files found.
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 162
+---Registers :
9 Bit Registers := 9
+---Muxes :
2 Input 9 Bit Muxes := 520
8 Input 9 Bit Muxes := 1
4 Input 9 Bit Muxes := 4
2 Input 4 Bit Muxes := 2
4 Input 4 Bit Muxes := 2
16 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 2
16 Input 3 Bit Muxes := 1
16 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 513
16 Input 1 Bit Muxes := 8
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module dataMemory
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 512
2 Input 1 Bit Muxes := 512
Module instructionMemory
Detailed RTL Component Info :
+---Muxes :
8 Input 9 Bit Muxes := 1
Module decoder__1
Detailed RTL Component Info :
+---Muxes :
2 Input 4 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
Module register__8
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module register__7
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module register__6
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module register__5
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module mux_4_1__3
Detailed RTL Component Info :
+---Muxes :
4 Input 9 Bit Muxes := 1
Module mux_4_1__2
Detailed RTL Component Info :
+---Muxes :
4 Input 9 Bit Muxes := 1
Module decoder
Detailed RTL Component Info :
+---Muxes :
2 Input 4 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
Module register__2
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module register__3
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module register__4
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module register
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module mux_4_1__1
Detailed RTL Component Info :
+---Muxes :
4 Input 9 Bit Muxes := 1
Module mux_4_1
Detailed RTL Component Info :
+---Muxes :
4 Input 9 Bit Muxes := 1
Module register__1
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module add_1bit__44
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__43
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__42
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__41
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__40
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__39
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__38
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__37
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__36
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module mux_2_1__1
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
Module add_1bit__35
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__34
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__33
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__32
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__31
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__30
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__29
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__28
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__27
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__62
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__61
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__60
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__59
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__58
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__57
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__56
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__55
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__54
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__26
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__25
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__24
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__23
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__22
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__21
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__20
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__19
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__18
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__80
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__79
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__78
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__77
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__76
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__75
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__74
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__73
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__72
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__71
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__70
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__69
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__68
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__67
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__66
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__65
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__64
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__63
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module ControlUnit
Detailed RTL Component Info :
+---Muxes :
16 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 2
16 Input 3 Bit Muxes := 1
16 Input 2 Bit Muxes := 1
16 Input 1 Bit Muxes := 8
Module add_1bit__53
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__52
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__51
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__50
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__49
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__48
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__47
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__46
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__45
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module mux_2_1__2
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
Module add_1bit__17
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__16
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__15
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__14
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__13
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__12
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__11
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__10
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__9
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module mux_2_1__3
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
Module mux_2_1__4
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
Module bit1_mux_2_1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module add_1bit__1
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__2
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__3
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__4
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__5
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__6
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__7
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit__8
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module add_1bit
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module mux_2_1__5
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
Module mux_2_1__6
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
Module mux_2_1__7
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
Module mux_2_1
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 600 (col length:100)
BRAMs: 650 (col length: RAMB18 100 RAMB36 50)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
No constraint files found.
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
INFO: [Synth 8-3886] merging instance 'CPU9bits0i_1/iM/readData_reg[0]' (LD) to 'CPU9bits0i_1/iM/readData_reg[2]'
INFO: [Synth 8-3886] merging instance 'CPU9bits0i_1/iM/readData_reg[8]' (LD) to 'CPU9bits0i_1/iM/readData_reg[6]'
INFO: [Synth 8-3886] merging instance 'CPU9bits0i_1/iM/readData_reg[2]' (LD) to 'CPU9bits0i_1/iM/readData_reg[4]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\iM/readData_reg[4] )
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:09:23 ; elapsed = 00:09:37 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
No constraint files found.
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:09:23 ; elapsed = 00:09:37 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:09:23 ; elapsed = 00:09:37 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+-+-----+------+
| |Cell |Count |
+-+-----+------+
+-+-----+------+
Report Instance Areas:
+------+---------+-------+------+
| |Instance |Module |Cells |
+------+---------+-------+------+
|1 |top | | 0|
+------+---------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 526 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
Synthesis Optimization Complete : Time (s): cpu = 00:09:24 ; elapsed = 00:09:38 . Memory (MB): peak = 3340.348 ; gain = 3082.594
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3340.348 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
177 Infos, 111 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:09:36 ; elapsed = 00:10:01 . Memory (MB): peak = 3340.348 ; gain = 3090.086
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 3340.348 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_tb_utilization_synth.rpt -pb CPU9bits_tb_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sun Mar 24 18:38:37 2019...

BIN
lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.pb Normal file
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Binary file not shown.

183
lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt Normal file
View File

@@ -0,0 +1,183 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sun Mar 24 16:58:30 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
| Design : CPU9bits
| Device : 7k160tifbg484-2L
| Design State : Synthesized
-----------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 578 | 0 | 101400 | 0.57 |
| LUT as Logic | 578 | 0 | 101400 | 0.57 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 235 | 0 | 202800 | 0.12 |
| Register as Flip Flop | 81 | 0 | 202800 | 0.04 |
| Register as Latch | 154 | 0 | 202800 | 0.08 |
| F7 Muxes | 6 | 0 | 50700 | 0.01 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 154 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 81 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 325 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
| RAMB18 | 0 | 0 | 650 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 600 | 0.00 |
+-----------+------+-------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 3 | 0 | 285 | 1.05 |
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
| PHASER_REF | 0 | 0 | 8 | 0.00 |
| OUT_FIFO | 0 | 0 | 32 | 0.00 |
| IN_FIFO | 0 | 0 | 32 | 0.00 |
| IDELAYCTRL | 0 | 0 | 8 | 0.00 |
| IBUFDS | 0 | 0 | 275 | 0.00 |
| GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 |
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 285 | 0.00 |
| OLOGIC | 0 | 0 | 285 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
5. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 2 | 0 | 32 | 6.25 |
| BUFIO | 0 | 0 | 32 | 0.00 |
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
| BUFMRCE | 0 | 0 | 16 | 0.00 |
| BUFHCE | 0 | 0 | 120 | 0.00 |
| BUFR | 0 | 0 | 32 | 0.00 |
+------------+------+-------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
7. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT6 | 439 | LUT |
| LDCE | 154 | Flop & Latch |
| FDRE | 81 | Flop & Latch |
| LUT5 | 69 | LUT |
| LUT4 | 51 | LUT |
| LUT3 | 50 | LUT |
| LUT2 | 45 | LUT |
| MUXF7 | 6 | MuxFx |
| IBUF | 2 | IO |
| BUFG | 2 | Clock |
| OBUF | 1 | IO |
+----------+------+---------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+

2
lab2CA.runs/synth_1/htr.txt
View File

@@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status.
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
REM REM
vivado -log CPU9bits.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl vivado -log CPU9bits_tb.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl

2
lab2CA.sim/sim_1/behav/xsim/CPU9bits_tb.tcl
View File

@@ -8,4 +8,4 @@ if { [string length $curr_wave] == 0 } {
} }
} }
run 1000ns run 100000ns

12
lab2CA.sim/sim_1/behav/xsim/webtalk_11344.backup.jou Normal file
View File

@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sun Mar 24 17:25:06 2019
# Process ID: 11344
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou Normal file
View File

@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sun Mar 24 17:34:31 2019
# Process ID: 12056
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_13536.backup.jou Normal file
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@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sun Mar 24 17:24:25 2019
# Process ID: 13536
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace

BIN
lab2CA.sim/sim_1/behav/xsim/xelab.pb
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24
lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
View File

@@ -1,10 +1,10 @@
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/ webtalk_init -webtalk_dir C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/
webtalk_register_client -client project webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Sun Mar 24 17:04:55 2019" -context "software_version_and_target_device" webtalk_add_data -client project -key date_generated -value "Sun Mar 24 19:25:23 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
@@ -12,21 +12,21 @@ webtalk_add_data -client project -key target_family -value "not_applicable" -con
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "f67bb5263bf851bf9c1beaa84fe1017c" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "111" -context "software_version_and_target_device" webtalk_add_data -client project -key project_iteration -value "48" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" webtalk_add_data -client project -key cpu_speed -value "2395 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" webtalk_add_data -client project -key system_ram -value "17.000 GB" -context "user_environment"
webtalk_register_client -client xsim webtalk_register_client -client xsim
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "870 ns" -context "xsim\\usage" webtalk_add_data -client xsim -key runtime -value "50020 ns" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.05_sec" -context "xsim\\usage" webtalk_add_data -client xsim -key Simulation_Time -value "0.30_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "6432_KB" -context "xsim\\usage" webtalk_add_data -client xsim -key Simulation_Memory -value "9684_KB" -context "xsim\\usage"
webtalk_transmit -clientid 2385566918 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>" webtalk_transmit -clientid 3966238694 -regid "" -xml C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate webtalk_terminate

BIN
lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
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12
lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml
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@@ -1,14 +1,14 @@
<?xml version="1.0" encoding="UTF-8" ?> <?xml version="1.0" encoding="UTF-8" ?>
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Sat Mar 16 14:04:40 2019'> <webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Sun Mar 24 17:35:36 2019'>
<section name="__ROOT__" level="0" order="1" description=""> <section name="__ROOT__" level="0" order="1" description="">
<section name="software_version_and_target_device" level="1" order="1" description=""> <section name="software_version_and_target_device" level="1" order="1" description="">
<keyValuePair key="beta" value="FALSE" description="" /> <keyValuePair key="beta" value="FALSE" description="" />
<keyValuePair key="build_version" value="2405991" description="" /> <keyValuePair key="build_version" value="2405991" description="" />
<keyValuePair key="date_generated" value="Sat Mar 16 14:04:39 2019" description="" /> <keyValuePair key="date_generated" value="Sun Mar 24 17:35:35 2019" description="" />
<keyValuePair key="os_platform" value="WIN64" description="" /> <keyValuePair key="os_platform" value="WIN64" description="" />
<keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" /> <keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" />
<keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" /> <keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" />
<keyValuePair key="project_iteration" value="2" description="" /> <keyValuePair key="project_iteration" value="21" description="" />
<keyValuePair key="random_id" value="4e917e26-7591-4435-9135-15bd446b0238" description="" /> <keyValuePair key="random_id" value="4e917e26-7591-4435-9135-15bd446b0238" description="" />
<keyValuePair key="registration_id" value="174150793_174150794_210688225_140" description="" /> <keyValuePair key="registration_id" value="174150793_174150794_210688225_140" description="" />
<keyValuePair key="route_design" value="FALSE" description="" /> <keyValuePair key="route_design" value="FALSE" description="" />
@@ -34,9 +34,9 @@
</section> </section>
<section name="usage" level="2" order="2" description=""> <section name="usage" level="2" order="2" description="">
<keyValuePair key="iteration" value="0" description="" /> <keyValuePair key="iteration" value="0" description="" />
<keyValuePair key="runtime" value="40 ns" description="" /> <keyValuePair key="runtime" value="60 ns" description="" />
<keyValuePair key="simulation_memory" value="6668_KB" description="" /> <keyValuePair key="simulation_memory" value="6100_KB" description="" />
<keyValuePair key="simulation_time" value="0.05_sec" description="" /> <keyValuePair key="simulation_time" value="0.03_sec" description="" />
<keyValuePair key="trace_waveform" value="true" description="" /> <keyValuePair key="trace_waveform" value="true" description="" />
</section> </section>
</section> </section>

10
lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl
View File

@@ -1,6 +1,6 @@
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/ webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/
webtalk_register_client -client project webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Sat Mar 16 14:16:46 2019" -context "software_version_and_target_device" webtalk_add_data -client project -key date_generated -value "Sun Mar 24 17:39:03 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
@@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "19" -context "software_version_and_target_device" webtalk_add_data -client project -key project_iteration -value "22" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment"
@@ -26,7 +26,7 @@ webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "60 ns" -context "xsim\\usage" webtalk_add_data -client xsim -key runtime -value "60 ns" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage" webtalk_add_data -client xsim -key Simulation_Time -value "0.05_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "6112_KB" -context "xsim\\usage" webtalk_add_data -client xsim -key Simulation_Memory -value "6128_KB" -context "xsim\\usage"
webtalk_transmit -clientid 2514989005 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>" webtalk_transmit -clientid 918939418 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate webtalk_terminate

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lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/xsim.mem
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12
lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml
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@@ -1,14 +1,14 @@
<?xml version="1.0" encoding="UTF-8" ?> <?xml version="1.0" encoding="UTF-8" ?>
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Sat Mar 16 13:13:49 2019'> <webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Sun Mar 24 17:25:06 2019'>
<section name="__ROOT__" level="0" order="1" description=""> <section name="__ROOT__" level="0" order="1" description="">
<section name="software_version_and_target_device" level="1" order="1" description=""> <section name="software_version_and_target_device" level="1" order="1" description="">
<keyValuePair key="beta" value="FALSE" description="" /> <keyValuePair key="beta" value="FALSE" description="" />
<keyValuePair key="build_version" value="2405991" description="" /> <keyValuePair key="build_version" value="2405991" description="" />
<keyValuePair key="date_generated" value="Sat Mar 16 13:13:48 2019" description="" /> <keyValuePair key="date_generated" value="Sun Mar 24 17:25:05 2019" description="" />
<keyValuePair key="os_platform" value="WIN64" description="" /> <keyValuePair key="os_platform" value="WIN64" description="" />
<keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" /> <keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" />
<keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" /> <keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" />
<keyValuePair key="project_iteration" value="2" description="" /> <keyValuePair key="project_iteration" value="6" description="" />
<keyValuePair key="random_id" value="4e917e26-7591-4435-9135-15bd446b0238" description="" /> <keyValuePair key="random_id" value="4e917e26-7591-4435-9135-15bd446b0238" description="" />
<keyValuePair key="registration_id" value="174150793_174150794_210688225_140" description="" /> <keyValuePair key="registration_id" value="174150793_174150794_210688225_140" description="" />
<keyValuePair key="route_design" value="FALSE" description="" /> <keyValuePair key="route_design" value="FALSE" description="" />
@@ -34,9 +34,9 @@
</section> </section>
<section name="usage" level="2" order="2" description=""> <section name="usage" level="2" order="2" description="">
<keyValuePair key="iteration" value="0" description="" /> <keyValuePair key="iteration" value="0" description="" />
<keyValuePair key="runtime" value="30 ns" description="" /> <keyValuePair key="runtime" value="45 ns" description="" />
<keyValuePair key="simulation_memory" value="6648_KB" description="" /> <keyValuePair key="simulation_memory" value="6100_KB" description="" />
<keyValuePair key="simulation_time" value="0.05_sec" description="" /> <keyValuePair key="simulation_time" value="0.03_sec" description="" />
<keyValuePair key="trace_waveform" value="true" description="" /> <keyValuePair key="trace_waveform" value="true" description="" />
</section> </section>
</section> </section>

12
lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl
View File

@@ -1,6 +1,6 @@
webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/ webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/
webtalk_register_client -client project webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Sat Mar 16 13:18:24 2019" -context "software_version_and_target_device" webtalk_add_data -client project -key date_generated -value "Sun Mar 24 17:39:06 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
@@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" webtalk_add_data -client project -key project_iteration -value "16" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment"
@@ -24,9 +24,9 @@ webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "us
webtalk_register_client -client xsim webtalk_register_client -client xsim
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "40 ns" -context "xsim\\usage" webtalk_add_data -client xsim -key runtime -value "45 ns" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage" webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "6108_KB" -context "xsim\\usage" webtalk_add_data -client xsim -key Simulation_Memory -value "6124_KB" -context "xsim\\usage"
webtalk_transmit -clientid 3866550317 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>" webtalk_transmit -clientid 643401725 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate webtalk_terminate

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lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/xsim.mem
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2
lab2CA.srcs/sources_1/new/CPU9bits.v
View File

@@ -190,7 +190,7 @@ module CPU9bits_tb();
reset = 1'b1; reset = 1'b1;
#10 #10
reset = 1'b0; reset = 1'b0;
#850 #50000

25
lab2CA.srcs/sources_1/new/dataMemory.v
View File

@@ -6,27 +6,10 @@ module dataMemory(
output reg [8:0] readData output reg [8:0] readData
); );
reg [8:0] memory [15:0]; reg [8:0] memory [23:0];
initial begin initial begin
// String Compare Memory // String Compare Memory
memory[0] <= 9'b000000100;
memory[1] <= 9'b000001000;
memory[2] <= 9'b000001100;
memory[3] <= 9'b010101010;
memory[4] <= 9'b000001111;
memory[5] <= 9'b000000100;
memory[6] <= 9'b000000011;
memory[7] <= 9'b000000111;
memory[8] <= 9'b000001111;
memory[9] <= 9'b000000100;
memory[10] <= 9'b000000010;
memory[11] <= 9'b000000000;
memory[12] <= 9'b000000000;
memory[13] <= 9'b000000000;
memory[14] <= 9'b000000000;
memory[15] <= 9'b000000000;
// // String Compare Memory
// memory[0] <= 9'b000000100; // memory[0] <= 9'b000000100;
// memory[1] <= 9'b000001000; // memory[1] <= 9'b000001000;
// memory[2] <= 9'b000001100; // memory[2] <= 9'b000001100;
@@ -34,7 +17,7 @@ module dataMemory(
// memory[4] <= 9'b000001111; // memory[4] <= 9'b000001111;
// memory[5] <= 9'b000000100; // memory[5] <= 9'b000000100;
// memory[6] <= 9'b000000011; // memory[6] <= 9'b000000011;
// memory[7] <= 9'b000000000; // memory[7] <= 9'b000000111;
// memory[8] <= 9'b000001111; // memory[8] <= 9'b000001111;
// memory[9] <= 9'b000000100; // memory[9] <= 9'b000000100;
// memory[10] <= 9'b000000010; // memory[10] <= 9'b000000010;
@@ -46,8 +29,8 @@ module dataMemory(
// Bubble Sort Initial Memory // Bubble Sort Initial Memory
memory[0] <= 9'b000011000; memory[0] <= 9'b000010110;
memory[1] <= 9'b000000000; memory[1] <= 9'b000100010;
memory[2] <= 9'b000100000; memory[2] <= 9'b000100000;
memory[3] <= 9'b010001000; memory[3] <= 9'b010001000;
memory[4] <= 9'b010010000; memory[4] <= 9'b010010000;

205
lab2CA.srcs/sources_1/new/instructionMemory.v
View File

@@ -34,57 +34,16 @@ module instructionMemory(
//String Compare //String Compare
memory[0] <= 9'b000000000; // memory[0] <= 9'b000000000;
memory[1] <= 9'b010000000; // memory[1] <= 9'b010000000;
memory[2] <= 9'b010001000; // memory[2] <= 9'b010001000;
memory[3] <= 9'b010010000; // memory[3] <= 9'b010010000;
memory[4] <= 9'b010011000; // memory[4] <= 9'b010011000;
memory[5] <= 9'b000100000; // memory[5] <= 9'b000100000;
memory[6] <= 9'b011001001; // memory[6] <= 9'b011001001;
memory[7] <= 9'b000101010; // memory[7] <= 9'b000101010;
memory[8] <= 9'b011010010; // memory[8] <= 9'b011010010;
memory[9] <= 9'b000110100; // memory[9] <= 9'b000110100;
memory[10] <= 9'b011011011;
memory[11] <= 9'b000111110;
memory[12] <= 9'b101010000;
memory[13] <= 9'b101000010;
memory[14] <= 9'b101001100;
memory[15] <= 9'b101011110; //ends initialization
memory[16] <= 9'b101000011;
memory[17] <= 9'b101001101;
memory[18] <= 9'b000110000;
memory[19] <= 9'b000111010;
memory[20] <= 9'b110010001;
memory[21] <= 9'b100100001;
memory[22] <= 9'b100110000;
memory[23] <= 9'b110011001;
memory[24] <= 9'b100100001;
memory[25] <= 9'b100101101;
memory[26] <= 9'b011000001;
memory[27] <= 9'b011001001;
memory[28] <= 9'b101000010;
memory[29] <= 9'b101001100;
memory[30] <= 9'b010110111;
memory[31] <= 9'b110010001;
memory[32] <= 9'b101110001;
memory[33] <= 9'b101000001;
memory[34] <= 9'b101001111;
memory[35] <= 9'b001001000;
memory[36] <= 9'b011000001;
memory[37] <= 9'b101000000;
memory[38] <= 9'b101110111;
memory[39] <= 9'b000000000;
// memory[0] <= 9'b000000000;
// memory[1] <= 9'b010000000;
// memory[2] <= 9'b010001000;
// memory[3] <= 9'b010010000;
// memory[4] <= 9'b010011000;
// memory[5] <= 9'b000100000;
// memory[6] <= 9'b011001001;
// memory[7] <= 9'b000101010;
// memory[8] <= 9'b011010010;
// memory[9] <= 9'b000110100;
// memory[10] <= 9'b011011011; // memory[10] <= 9'b011011011;
// memory[11] <= 9'b000111110; // memory[11] <= 9'b000111110;
// memory[12] <= 9'b101010000; // memory[12] <= 9'b101010000;
@@ -107,13 +66,13 @@ module instructionMemory(
// memory[29] <= 9'b101001100; // memory[29] <= 9'b101001100;
// memory[30] <= 9'b010110111; // memory[30] <= 9'b010110111;
// memory[31] <= 9'b110010001; // memory[31] <= 9'b110010001;
// memory[32] <= 9'b101110010; // memory[32] <= 9'b101110001;
// memory[33] <= 9'b101000000; // memory[33] <= 9'b101000001;
// memory[34] <= 9'b101001110; // memory[34] <= 9'b101001111;
// memory[35] <= 9'b001001000; // memory[35] <= 9'b001001000;
// memory[36] <= 9'b011000001; // memory[36] <= 9'b011000001;
// memory[37] <= 9'b101000000; // memory[37] <= 9'b101000000;
// memory[38] <= 9'b101111000; // memory[38] <= 9'b101110111;
// memory[39] <= 9'b000000000; // memory[39] <= 9'b000000000;
@@ -136,8 +95,8 @@ module instructionMemory(
// Check if at the end of the array // Check if at the end of the array
// EndChk: // EndChk:
memory[12] <= 9'b101001001; // bankl $b, $0 memory[12] <= 9'b101001001; // bankl $b, $0
memory[13] <= 9'b011101000; // slt $b, $a memory[13] <= 9'b011101000; // slt $b, $a
memory[14] <= 9'b110001010; // beq $b, JSC memory[14] <= 9'b110001001; // beq $b, JSC
memory[15] <= 9'b100100001; // jf LoadNext memory[15] <= 9'b100100001; // jf LoadNext
// JSC: // JSC:
memory[16] <= 9'b100110100; // jf SwapChk memory[16] <= 9'b100110100; // jf SwapChk
@@ -150,8 +109,8 @@ module instructionMemory(
memory[21] <= 9'b000111010; // lb $d, $b memory[21] <= 9'b000111010; // lb $d, $b
// Compare loaded values to see if they need to be swapped // Compare loaded values to see if they need to be swapped
memory[22] <= 9'b101011110; // banks $d, $3 memory[22] <= 9'b101011110; // banks $d, $3
memory[23] <= 9'b011111100; // slt $d, $c memory[23] <= 9'b011111100; // slt $d, $c
memory[24] <= 9'b110011010; // beq $d, JI memory[24] <= 9'b110011001; // beq $d, JI
memory[25] <= 9'b100100001; // jf Swap memory[25] <= 9'b100100001; // jf Swap
// JI: // JI:
memory[26] <= 9'b101110010; // jb Inc memory[26] <= 9'b101110010; // jb Inc
@@ -170,7 +129,7 @@ module instructionMemory(
// Check to see if any swaps have been made in the last iteration // Check to see if any swaps have been made in the last iteration
// SwapChk: // SwapChk:
memory[37] <= 9'b101001011; // bankl $b, $1 memory[37] <= 9'b101001011; // bankl $b, $1
memory[38] <= 9'b110001001; // beq $b, JE memory[38] <= 9'b110001001; // beq $b, JE
memory[39] <= 9'b100100001; // jf Reset memory[39] <= 9'b100100001; // jf Reset
// JE: // JE:
memory[40] <= 9'b100100011; // jf End memory[40] <= 9'b100100011; // jf End
@@ -184,69 +143,69 @@ module instructionMemory(
// Binary Search // Binary Search
memory[0] <= 9'b000000000; // memory[0] <= 9'b000000000;
memory[1] <= 9'b000000000; // memory[1] <= 9'b000000000;
memory[2] <= 9'b000000000; // memory[2] <= 9'b000000000;
memory[3] <= 9'b000000000; // memory[3] <= 9'b000000000;
memory[4] <= 9'b000000000; // memory[4] <= 9'b000000000;
memory[5] <= 9'b011001011; //addi R1, 3 (N = 3) // memory[5] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[6] <= 9'b011001011; //addi R1, 3 (N = 3) // memory[6] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[7] <= 9'b011001011; //addi R1, 3 (N = 3) // memory[7] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[8] <= 9'b011001011; //addi R1, 3 (N = 3) // memory[8] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[9] <= 9'b011001011; //addi R1, 3 (N = 3) // memory[9] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[10] <= 9'b011011010; //addi R3, 2 (inputAddr = 2) // memory[10] <= 9'b011011010; //addi R3, 2 (inputAddr = 2)
memory[11] <= 9'b000111110; //lb R3, R3 // memory[11] <= 9'b000111110; //lb R3, R3
memory[12] <= 9'b101011010; //banks R3, 1 // memory[12] <= 9'b101011010; //banks R3, 1
memory[13] <= 9'b011001011; //addi R1, 3 (N = 3) // memory[13] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[14] <= 9'b101000000; //loop: banks R0, 0 // memory[14] <= 9'b101000000; //loop: banks R0, 0
memory[15] <= 9'b011100010; //slt R0, R1 // memory[15] <= 9'b011100010; //slt R0, R1
memory[16] <= 9'b110000001; //beq R0, Exit // memory[16] <= 9'b110000001; //beq R0, Exit
memory[17] <= 9'b100100001; //j Skip0 // memory[17] <= 9'b100100001; //j Skip0
memory[18] <= 9'b100101111; //Exit: j Loose // memory[18] <= 9'b100101111; //Exit: j Loose
memory[19] <= 9'b101000001; //Skip0: bankl R0, 0 // memory[19] <= 9'b101000001; //Skip0: bankl R0, 0
memory[20] <= 9'b010110000; //add R2, R0 // memory[20] <= 9'b010110000; //add R2, R0
memory[21] <= 9'b010110010; //add R2, R1 // memory[21] <= 9'b010110010; //add R2, R1
memory[22] <= 9'b111110001; //srl R2 // memory[22] <= 9'b111110001; //srl R2
memory[23] <= 9'b101011011; //bankl R3,1 // memory[23] <= 9'b101011011; //bankl R3,1
memory[24] <= 9'b010111100; //add R3, R2 // memory[24] <= 9'b010111100; //add R3, R2
memory[25] <= 9'b101001100; //banks R1, 2 // memory[25] <= 9'b101001100; //banks R1, 2
memory[26] <= 9'b000100110; //lb R0, R3 // memory[26] <= 9'b000100110; //lb R0, R3
memory[27] <= 9'b010001000; //zero R1 // memory[27] <= 9'b010001000; //zero R1
memory[28] <= 9'b011001001; //addi R1, 1 (numAddr = 1) // memory[28] <= 9'b011001001; //addi R1, 1 (numAddr = 1)
memory[29] <= 9'b000101010; //lb R1, R1 // memory[29] <= 9'b000101010; //lb R1, R1
memory[30] <= 9'b100100001; //j SkipU // memory[30] <= 9'b100100001; //j SkipU
memory[31] <= 9'b101110010; //j TransLoop // memory[31] <= 9'b101110010; //j TransLoop
memory[32] <= 9'b101010110; //SkipU: banks R2, 3 // memory[32] <= 9'b101010110; //SkipU: banks R2, 3
memory[33] <= 9'b100100001; //j SkipD // memory[33] <= 9'b100100001; //j SkipD
memory[34] <= 9'b100110111; //j TransLoose // memory[34] <= 9'b100110111; //j TransLoose
memory[35] <= 9'b010010000; //SkipD: zero R2 // memory[35] <= 9'b010010000; //SkipD: zero R2
memory[36] <= 9'b010110010; //add R2, R1 // memory[36] <= 9'b010110010; //add R2, R1
memory[37] <= 9'b010101001; //sub R1, R0 // memory[37] <= 9'b010101001; //sub R1, R0
memory[38] <= 9'b110001001; //beq R1, Go1 // memory[38] <= 9'b110001001; //beq R1, Go1
memory[39] <= 9'b100100001; //j Skip1 // memory[39] <= 9'b100100001; //j Skip1
memory[40] <= 9'b100101001; //Go1: j Win // memory[40] <= 9'b100101001; //Go1: j Win
memory[41] <= 9'b010001000; //Skip1: zero R1 // memory[41] <= 9'b010001000; //Skip1: zero R1
memory[42] <= 9'b010101100; //add R1, R2 // memory[42] <= 9'b010101100; //add R1, R2
memory[43] <= 9'b011100010; //slt R0, R1 // memory[43] <= 9'b011100010; //slt R0, R1
memory[44] <= 9'b110000001; //beq R0, Go2 // memory[44] <= 9'b110000001; //beq R0, Go2
memory[45] <= 9'b100100110; //j Skip2 // memory[45] <= 9'b100100110; //j Skip2
memory[46] <= 9'b010000000; //Go2: zero R0 // memory[46] <= 9'b010000000; //Go2: zero R0
memory[47] <= 9'b011000001; //addi R0, 1 // memory[47] <= 9'b011000001; //addi R0, 1
memory[48] <= 9'b101001111; //bankl R1,3 // memory[48] <= 9'b101001111; //bankl R1,3
memory[49] <= 9'b010100010; //add R0, R1 // memory[49] <= 9'b010100010; //add R0, R1
memory[50] <= 9'b101001101; //bankl R1,2 // memory[50] <= 9'b101001101; //bankl R1,2
memory[51] <= 9'b101110101; //j loop // memory[51] <= 9'b101110101; //j loop
memory[52] <= 9'b010001000; //Skip2: zero R1 // memory[52] <= 9'b010001000; //Skip2: zero R1
memory[53] <= 9'b011001111; //addi R1, -1 // memory[53] <= 9'b011001111; //addi R1, -1
memory[54] <= 9'b101000111; //bankl R0, 3 // memory[54] <= 9'b101000111; //bankl R0, 3
memory[55] <= 9'b010101000; //add R1, R0 // memory[55] <= 9'b010101000; //add R1, R0
memory[56] <= 9'b101000001; //bankl R0,0 // memory[56] <= 9'b101000001; //bankl R0,0
memory[57] <= 9'b101111011; //j loop // memory[57] <= 9'b101111011; //j loop
memory[58] <= 9'b010000000; //Loose: zero R0 // memory[58] <= 9'b010000000; //Loose: zero R0
memory[59] <= 9'b011000111; //addi R0, -1 // memory[59] <= 9'b011000111; //addi R0, -1
memory[60] <= 9'b101000110; //banks R0, 3 // memory[60] <= 9'b101000110; //banks R0, 3
memory[61] <= 9'b100100000; //j Win // memory[61] <= 9'b100100000; //j Win
memory[62] <= 9'b000000000; //Win: halt // memory[62] <= 9'b000000000; //Win: halt
end end

16
lab2CA.xpr
View File

@@ -3,7 +3,7 @@
<!-- --> <!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --> <!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="39" Path="C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr"> <Project Version="7" Minor="39" Path="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr">
<DefaultLaunch Dir="$PRUNDIR"/> <DefaultLaunch Dir="$PRUNDIR"/>
<Configuration> <Configuration>
<Option Name="Id" Val="0a5803efda44405bb28bbf43ba22e808"/> <Option Name="Id" Val="0a5803efda44405bb28bbf43ba22e808"/>
@@ -31,7 +31,7 @@
<Option Name="EnableBDX" Val="FALSE"/> <Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/> <Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/> <Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="312"/> <Option Name="WTXSimLaunchSim" Val="338"/>
<Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/>
@@ -156,6 +156,7 @@
<Option Name="XSimWcfgFile" Val="$PPRDIR/regFile_tb_behav.wcfg"/> <Option Name="XSimWcfgFile" Val="$PPRDIR/regFile_tb_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/CPU9bits_tb_behav1.wcfg"/> <Option Name="XSimWcfgFile" Val="$PPRDIR/CPU9bits_tb_behav1.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/Bank_behav1.wcfg"/> <Option Name="XSimWcfgFile" Val="$PPRDIR/Bank_behav1.wcfg"/>
<Option Name="xsim.simulate.runtime" Val="100000ns"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1"> <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
@@ -186,16 +187,20 @@
<Runs Version="1" Minor="10"> <Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/> <Step Id="synth_design"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/> <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run> </Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/> <Step Id="init_design"/>
<Step Id="opt_design"/> <Step Id="opt_design"/>
<Step Id="power_opt_design"/> <Step Id="power_opt_design"/>
@@ -206,7 +211,6 @@
<Step Id="post_route_phys_opt_design"/> <Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/> <Step Id="write_bitstream"/>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/> <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run> </Run>