Renamed shifting for incoming shift_right_arithmetic

2019-03-12 10:54:45 -04:00
parent f3ea596086
commit 9e9ff7935b
2 changed files with 9 additions and 9 deletions
--- a/lab2CA.srcs/sources_1/new/ALU.v
+++ b/lab2CA.srcs/sources_1/new/ALU.v
@@ -36,12 +36,12 @@ module ALU(
        .A(operand0),
        .B(operand1),
        .C(result_E));
-    // F (101) - Shift Logical Left
-    shift_logical_left sll(
+    // F (101) - Shift Left
+    shift_left sl(
        .A(operand0),
        .B(result_F));
    // G (110) - Shift Logical Right
-    shift_logical_right slr(
+    shift_right_logical srl(
        .A(operand0),
        .B(result_G));
    // H (111) //slt