Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

# Conflicts:
#	CPU9bits_tb_behav.wcfg
#	lab2CA.srcs/sources_1/new/CPU9bits.v
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr

lab2CA.srcs/sources_1/new/dataMemory.v

@@ -6,14 +6,14 @@ module dataMemory(
     output reg [8:0] readData
     );
     
-    reg [8:0] memory [1:0];   // Maximum of 512 memory locations
+    reg [8:0] memory [100:0];   // Maximum of 512 memory locations
                                 // Vivado will give warnings of unconnected ports on the "address" bus if they are unused
     
     initial begin
 
 
 
-        //Equation Solver Memory
+        // Equation Solver Memory
 
         memory[0] <= 9'b000000001;
         memory[1] <= 9'b000000010;