Vivado stuff
This commit is contained in:
WilliamMiceli
@@ -3,7 +3,7 @@
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<!--The data in this file is primarily intended for consumption by Xilinx tools.
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The structure and the elements are likely to change over the next few releases.
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This means code written to parse this file will need to be revisited each subsequent release.-->
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<application name="pa" timeStamp="Sat Apr 6 14:02:34 2019">
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<application name="pa" timeStamp="Sat Apr 6 16:04:11 2019">
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<section name="Project Information" visible="false">
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<property name="ProjectID" value="88e779ed22f94d2db93b335d17c75f15" type="ProjectID"/>
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<property name="ProjectIteration" value="25" type="ProjectIteration"/>
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@@ -17,7 +17,7 @@ This means code written to parse this file will need to be revisited each subseq
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<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
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</item>
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<item name="Java Command Handlers">
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<property name="CloseProject" value="20" type="JavaHandler"/>
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<property name="CloseProject" value="23" type="JavaHandler"/>
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<property name="EditDelete" value="2" type="JavaHandler"/>
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<property name="FlipToViewTaskRTLAnalysis" value="1" type="JavaHandler"/>
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<property name="OpenDesign" value="1" type="JavaHandler"/>
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@@ -27,17 +27,17 @@ This means code written to parse this file will need to be revisited each subseq
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<property name="ReportTimingSummary" value="9" type="JavaHandler"/>
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<property name="RunImplementation" value="30" type="JavaHandler"/>
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<property name="RunSchematic" value="30" type="JavaHandler"/>
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<property name="RunSynthesis" value="34" type="JavaHandler"/>
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<property name="RunSynthesis" value="39" type="JavaHandler"/>
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<property name="SaveFileProxyHandler" value="2" type="JavaHandler"/>
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<property name="SaveLayoutAs" value="1" type="JavaHandler"/>
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<property name="SetSourceEnabled" value="5" type="JavaHandler"/>
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<property name="SetTopNode" value="42" type="JavaHandler"/>
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<property name="SetSourceEnabled" value="6" type="JavaHandler"/>
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<property name="SetTopNode" value="44" type="JavaHandler"/>
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<property name="ShowSimulationDefaultWaveFormView" value="1" type="JavaHandler"/>
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<property name="ShowSource" value="1" type="JavaHandler"/>
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<property name="ShowView" value="22" type="JavaHandler"/>
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<property name="SimulationClose" value="6" type="JavaHandler"/>
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<property name="SimulationRelaunch" value="100" type="JavaHandler"/>
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<property name="SimulationRun" value="97" type="JavaHandler"/>
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<property name="ShowView" value="32" type="JavaHandler"/>
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<property name="SimulationClose" value="7" type="JavaHandler"/>
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<property name="SimulationRelaunch" value="107" type="JavaHandler"/>
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<property name="SimulationRun" value="102" type="JavaHandler"/>
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<property name="SimulationRunForTime" value="3" type="JavaHandler"/>
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<property name="TclFind" value="6" type="JavaHandler"/>
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<property name="ToggleSelectAreaMode" value="2" type="JavaHandler"/>
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@@ -46,11 +46,11 @@ This means code written to parse this file will need to be revisited each subseq
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<property name="UpdateSourceFiles" value="1" type="JavaHandler"/>
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<property name="ViewLayoutCmd" value="2" type="JavaHandler"/>
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<property name="ViewTaskImplementation" value="4" type="JavaHandler"/>
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<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
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<property name="ViewTaskProjectManager" value="3" type="JavaHandler"/>
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<property name="ViewTaskRTLAnalysis" value="15" type="JavaHandler"/>
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<property name="WaveformOpenConfiguration" value="1" type="JavaHandler"/>
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<property name="WaveformRenameObject" value="2" type="JavaHandler"/>
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<property name="WaveformSaveConfiguration" value="12" type="JavaHandler"/>
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<property name="WaveformSaveConfiguration" value="14" type="JavaHandler"/>
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<property name="WaveformSaveConfigurationAs" value="1" type="JavaHandler"/>
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<property name="ZoomFit" value="10" type="JavaHandler"/>
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<property name="ZoomOut" value="3" type="JavaHandler"/>
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@@ -61,45 +61,45 @@ This means code written to parse this file will need to be revisited each subseq
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<property name="BaseDialogUtils_OPEN_IN_SPECIFIED_LAYOUT" value="1" type="GuiHandlerData"/>
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<property name="BaseDialog_APPLY" value="1" type="GuiHandlerData"/>
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<property name="BaseDialog_CANCEL" value="32" type="GuiHandlerData"/>
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<property name="BaseDialog_OK" value="135" type="GuiHandlerData"/>
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<property name="BaseDialog_OK" value="137" type="GuiHandlerData"/>
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<property name="BaseDialog_YES" value="20" type="GuiHandlerData"/>
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<property name="ClosePlanner_YES" value="1" type="GuiHandlerData"/>
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<property name="CmdMsgDialog_MESSAGES" value="2" type="GuiHandlerData"/>
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<property name="CmdMsgDialog_OK" value="13" type="GuiHandlerData"/>
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<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="2" type="GuiHandlerData"/>
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<property name="CmdMsgDialog_OK" value="14" type="GuiHandlerData"/>
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<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="4" type="GuiHandlerData"/>
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<property name="CodeView_TOGGLE_COLUMN_SELECTION_MODE" value="14" type="GuiHandlerData"/>
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<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="539" type="GuiHandlerData"/>
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<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="577" type="GuiHandlerData"/>
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<property name="FloatingTopDialog_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="12" type="GuiHandlerData"/>
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<property name="FloatingTopDialog_SPECIFY_NEW_TOP_MODULE" value="10" type="GuiHandlerData"/>
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<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="290" type="GuiHandlerData"/>
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<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="307" type="GuiHandlerData"/>
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<property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
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<property name="GraphicalView_ZOOM_FIT" value="67" type="GuiHandlerData"/>
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<property name="GraphicalView_ZOOM_IN" value="47" type="GuiHandlerData"/>
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<property name="GraphicalView_ZOOM_OUT" value="35" type="GuiHandlerData"/>
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<property name="GraphicalView_ZOOM_IN" value="48" type="GuiHandlerData"/>
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<property name="GraphicalView_ZOOM_OUT" value="36" type="GuiHandlerData"/>
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<property name="HCodeEditor_BLANK_OPERATIONS" value="6" type="GuiHandlerData"/>
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<property name="HCodeEditor_CLOSE" value="9" type="GuiHandlerData"/>
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<property name="HCodeEditor_CLOSE" value="10" type="GuiHandlerData"/>
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<property name="HCodeEditor_COMMANDS_TO_FOLD_TEXT" value="3" type="GuiHandlerData"/>
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<property name="HCodeEditor_DIFF_WITH" value="3" type="GuiHandlerData"/>
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<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="58" type="GuiHandlerData"/>
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<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="62" type="GuiHandlerData"/>
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<property name="HInputHandler_INDENT_SELECTION" value="1" type="GuiHandlerData"/>
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<property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="15" type="GuiHandlerData"/>
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<property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
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<property name="InstanceMenu_FLOORPLANNING" value="2" type="GuiHandlerData"/>
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<property name="LaunchPanel_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
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<property name="MainMenuMgr_CHECKPOINT" value="6" type="GuiHandlerData"/>
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<property name="MainMenuMgr_CHECKPOINT" value="7" type="GuiHandlerData"/>
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<property name="MainMenuMgr_CONSTRAINTS" value="2" type="GuiHandlerData"/>
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<property name="MainMenuMgr_EDIT" value="10" type="GuiHandlerData"/>
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<property name="MainMenuMgr_EXPORT" value="5" type="GuiHandlerData"/>
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<property name="MainMenuMgr_FILE" value="62" type="GuiHandlerData"/>
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<property name="MainMenuMgr_FILE" value="68" type="GuiHandlerData"/>
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<property name="MainMenuMgr_FLOW" value="8" type="GuiHandlerData"/>
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<property name="MainMenuMgr_IP" value="6" type="GuiHandlerData"/>
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<property name="MainMenuMgr_IP" value="7" type="GuiHandlerData"/>
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<property name="MainMenuMgr_OPEN_BLOCK_DESIGN" value="2" type="GuiHandlerData"/>
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<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="2" type="GuiHandlerData"/>
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<property name="MainMenuMgr_PROJECT" value="31" type="GuiHandlerData"/>
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<property name="MainMenuMgr_PROJECT" value="32" type="GuiHandlerData"/>
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<property name="MainMenuMgr_REPORTS" value="4" type="GuiHandlerData"/>
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<property name="MainMenuMgr_RUN" value="2" type="GuiHandlerData"/>
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<property name="MainMenuMgr_SETTINGS" value="2" type="GuiHandlerData"/>
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<property name="MainMenuMgr_SIMULATION_WAVEFORM" value="13" type="GuiHandlerData"/>
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<property name="MainMenuMgr_SIMULATION_WAVEFORM" value="16" type="GuiHandlerData"/>
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<property name="MainMenuMgr_TEXT_EDITOR" value="7" type="GuiHandlerData"/>
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<property name="MainMenuMgr_TOOLS" value="6" type="GuiHandlerData"/>
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<property name="MainMenuMgr_VIEW" value="2" type="GuiHandlerData"/>
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@@ -109,7 +109,7 @@ This means code written to parse this file will need to be revisited each subseq
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<property name="MainWinToolbarMgr_SELECT_OR_SAVE_WINDOW_LAYOUT" value="3" type="GuiHandlerData"/>
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<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="6" type="GuiHandlerData"/>
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<property name="MsgTreePanel_MESSAGE_SEVERITY" value="2" type="GuiHandlerData"/>
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<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="153" type="GuiHandlerData"/>
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<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="162" type="GuiHandlerData"/>
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<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="5" type="GuiHandlerData"/>
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<property name="MsgView_WARNING_MESSAGES" value="3" type="GuiHandlerData"/>
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<property name="NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE" value="117" type="GuiHandlerData"/>
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@@ -119,8 +119,8 @@ This means code written to parse this file will need to be revisited each subseq
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<property name="NetlistTreeView_NETLIST_TREE" value="4" type="GuiHandlerData"/>
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<property name="OpenFileAction_CANCEL" value="2" type="GuiHandlerData"/>
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<property name="OpenFileAction_OK" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_AUTO_UPDATE_HIER" value="51" type="GuiHandlerData"/>
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<property name="PACommandNames_CLOSE_PROJECT" value="19" type="GuiHandlerData"/>
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<property name="PACommandNames_AUTO_UPDATE_HIER" value="52" type="GuiHandlerData"/>
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<property name="PACommandNames_CLOSE_PROJECT" value="22" type="GuiHandlerData"/>
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<property name="PACommandNames_GOTO_INSTANTIATION" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_MESSAGE_WINDOW" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
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@@ -128,26 +128,26 @@ This means code written to parse this file will need to be revisited each subseq
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<property name="PACommandNames_RELOAD_RTL_DESIGN" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_SCHEMATIC" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_SELECT_AREA" value="2" type="GuiHandlerData"/>
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<property name="PACommandNames_SET_AS_TOP" value="43" type="GuiHandlerData"/>
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<property name="PACommandNames_SET_AS_TOP" value="45" type="GuiHandlerData"/>
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<property name="PACommandNames_SIMULATION_CLOSE" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_SIMULATION_DEFAULT_WAVEFORM_WINDOW" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_SIMULATION_LIVE_RUN" value="4" type="GuiHandlerData"/>
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<property name="PACommandNames_SIMULATION_RELAUNCH" value="107" type="GuiHandlerData"/>
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<property name="PACommandNames_SIMULATION_RELAUNCH" value="114" type="GuiHandlerData"/>
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<property name="PACommandNames_SIMULATION_RUN" value="3" type="GuiHandlerData"/>
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<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="96" type="GuiHandlerData"/>
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<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="101" type="GuiHandlerData"/>
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<property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_FUNCTIONAL" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_TIMING" value="4" type="GuiHandlerData"/>
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<property name="PACommandNames_SIMULATION_SETTINGS" value="2" type="GuiHandlerData"/>
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<property name="PACommandNames_SRC_DISABLE" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_SRC_DISABLE" value="2" type="GuiHandlerData"/>
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<property name="PACommandNames_SRC_ENABLE" value="3" type="GuiHandlerData"/>
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<property name="PACommandNames_SRC_REPLACE_FILE" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_TOGGLE_VIEW_NAV" value="1" type="GuiHandlerData"/>
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<property name="PACommandNames_ZOOM_FIT" value="10" type="GuiHandlerData"/>
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<property name="PACommandNames_ZOOM_OUT" value="3" type="GuiHandlerData"/>
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<property name="PAViews_CODE" value="46" type="GuiHandlerData"/>
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<property name="PAViews_CODE" value="56" type="GuiHandlerData"/>
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<property name="PAViews_DEVICE" value="3" type="GuiHandlerData"/>
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<property name="PAViews_PATH_TABLE" value="1" type="GuiHandlerData"/>
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<property name="PAViews_PROJECT_SUMMARY" value="66" type="GuiHandlerData"/>
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<property name="PAViews_PROJECT_SUMMARY" value="71" type="GuiHandlerData"/>
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<property name="PAViews_SCHEMATIC" value="28" type="GuiHandlerData"/>
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<property name="PathReportTableView_DESCRIPTION" value="2" type="GuiHandlerData"/>
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<property name="PlanAheadTab_SHOW_FLOW_NAVIGATOR" value="2" type="GuiHandlerData"/>
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@@ -165,26 +165,26 @@ This means code written to parse this file will need to be revisited each subseq
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<property name="RDICommands_WAVEFORM_OPEN_CONFIGURATION" value="1" type="GuiHandlerData"/>
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<property name="RDICommands_WAVEFORM_SAVE_CONFIGURATION" value="5" type="GuiHandlerData"/>
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<property name="RDICommands_WAVEFORM_SAVE_CONFIGURATION_AS" value="1" type="GuiHandlerData"/>
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<property name="RDIViews_WAVEFORM_VIEWER" value="885" type="GuiHandlerData"/>
|
||||
<property name="RDIViews_WAVEFORM_VIEWER" value="898" type="GuiHandlerData"/>
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<property name="ReportTimingSummaryDialog_REPORT_TIMING_SUMMARY_DIALOG_TABBED" value="14" type="GuiHandlerData"/>
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||||
<property name="ReportTimingSummaryDialog_REPORT_UNCONSTRAINED_PATHS" value="6" type="GuiHandlerData"/>
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||||
<property name="RunGadget_SHOW_ERROR" value="1" type="GuiHandlerData"/>
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||||
<property name="RunGadget_SHOW_WARNING_AND_ERROR_MESSAGES_IN_MESSAGES" value="4" type="GuiHandlerData"/>
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<property name="RunGadget_SHOW_WARNING_AND_ERROR_MESSAGES_IN_MESSAGES" value="6" type="GuiHandlerData"/>
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||||
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="12" type="GuiHandlerData"/>
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<property name="SaveProjectUtils_SAVE" value="13" type="GuiHandlerData"/>
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||||
<property name="SelectMenu_HIGHLIGHT" value="2" type="GuiHandlerData"/>
|
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<property name="SelectMenu_MARK" value="2" type="GuiHandlerData"/>
|
||||
<property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="12" type="GuiHandlerData"/>
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||||
<property name="SimulationForceSettingsDialog_FORCE_VALUE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimulationForceSettingsDialog_VALUE_RADIX" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimulationLiveRunForComp_SPECIFY_TIME_AND_UNITS" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="85" type="GuiHandlerData"/>
|
||||
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="154" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_HIERARCHY" value="50" type="GuiHandlerData"/>
|
||||
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="88" type="GuiHandlerData"/>
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||||
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="188" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_HIERARCHY" value="53" type="GuiHandlerData"/>
|
||||
<property name="StaleMoreAction_OUT_OF_DATE_DETAILS" value="1" type="GuiHandlerData"/>
|
||||
<property name="StaleRunDialog_NO" value="3" type="GuiHandlerData"/>
|
||||
<property name="StaleRunDialog_YES" value="1" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="31" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="35" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaStateMonitor_CANCEL" value="2" type="GuiHandlerData"/>
|
||||
<property name="TaskBanner_CLOSE" value="41" type="GuiHandlerData"/>
|
||||
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/>
|
||||
@@ -192,7 +192,7 @@ This means code written to parse this file will need to be revisited each subseq
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||||
<property name="TimingDialogUtils_RESULTS_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="TimingItemFlatTablePanel_TABLE" value="3" type="GuiHandlerData"/>
|
||||
<property name="WaveformFindBar_CLOSE" value="1" type="GuiHandlerData"/>
|
||||
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="543" type="GuiHandlerData"/>
|
||||
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="610" type="GuiHandlerData"/>
|
||||
<property name="WaveformView_GOTO_CURSOR" value="3" type="GuiHandlerData"/>
|
||||
<property name="WaveformView_GOTO_LAST_TIME" value="1" type="GuiHandlerData"/>
|
||||
<property name="WaveformView_GOTO_TIME_0" value="8" type="GuiHandlerData"/>
|
||||
|
||||
8
lab2CA.runs/.jobs/vrs_config_63.xml
Normal file
8
lab2CA.runs/.jobs/vrs_config_63.xml
Normal file
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
8
lab2CA.runs/.jobs/vrs_config_64.xml
Normal file
8
lab2CA.runs/.jobs/vrs_config_64.xml
Normal file
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
8
lab2CA.runs/.jobs/vrs_config_65.xml
Normal file
8
lab2CA.runs/.jobs/vrs_config_65.xml
Normal file
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
8
lab2CA.runs/.jobs/vrs_config_66.xml
Normal file
8
lab2CA.runs/.jobs/vrs_config_66.xml
Normal file
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
8
lab2CA.runs/.jobs/vrs_config_67.xml
Normal file
8
lab2CA.runs/.jobs/vrs_config_67.xml
Normal file
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
Binary file not shown.
BIN
lab2CA.runs/synth_1/CPU9bits_tb.dcp
Normal file
BIN
lab2CA.runs/synth_1/CPU9bits_tb.dcp
Normal file
Binary file not shown.
@@ -49,12 +49,12 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top CPU9bits -part xc7k160tifbg484-2L
|
||||
synth_design -top CPU9bits_tb -part xc7k160tifbg484-2L
|
||||
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef CPU9bits.dcp
|
||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb"
|
||||
write_checkpoint -force -noxdef CPU9bits_tb.dcp
|
||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file CPU9bits_tb_utilization_synth.rpt -pb CPU9bits_tb_utilization_synth.pb"
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
@@ -2,23 +2,25 @@
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Sat Apr 6 14:00:40 2019
|
||||
# Process ID: 8416
|
||||
# Start of session at: Sat Apr 6 16:04:16 2019
|
||||
# Process ID: 22928
|
||||
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
|
||||
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
|
||||
# Command line: vivado.exe -log CPU9bits_tb.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl
|
||||
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.vds
|
||||
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source CPU9bits.tcl -notrace
|
||||
Command: synth_design -top CPU9bits -part xc7k160tifbg484-2L
|
||||
source CPU9bits_tb.tcl -notrace
|
||||
Command: synth_design -top CPU9bits_tb -part xc7k160tifbg484-2L
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 19172
|
||||
INFO: Helper process launched with PID 23288
|
||||
---------------------------------------------------------------------------------
|
||||
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 362.617 ; gain = 101.777
|
||||
Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 362.297 ; gain = 100.883
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'CPU9bits_tb' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:204]
|
||||
WARNING: [Synth 8-85] always block has no event control specified [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:209]
|
||||
INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
|
||||
@@ -26,79 +28,82 @@ INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/REPOSITORIES/Education
|
||||
INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:266]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
|
||||
INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
|
||||
INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:766]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:766]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:396]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:401]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:396]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
|
||||
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:325]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:331]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:325]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
|
||||
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
|
||||
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
|
||||
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
|
||||
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
|
||||
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1334]
|
||||
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1399]
|
||||
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:676]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:676]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1399]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1334]
|
||||
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:713]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:713]
|
||||
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:632]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:632]
|
||||
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
|
||||
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
|
||||
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:876]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:876]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:950]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:950]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:913]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:913]
|
||||
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:309]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:309]
|
||||
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1448]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1448]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:524]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:530]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:524]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:13]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996]
|
||||
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
|
||||
INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1019]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1019]
|
||||
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:345]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (27#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
|
||||
WARNING: [Synth 8-350] instance 'CPU9bits0' of module 'CPU9bits' requires 4 connections, but only 3 given [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:212]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits_tb' (28#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:204]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port enable
|
||||
WARNING: [Synth 8-3331] design dataMemory has unconnected port address[8]
|
||||
WARNING: [Synth 8-3331] design dataMemory has unconnected port address[7]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.656 ; gain = 157.816
|
||||
Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.582 ; gain = 157.168
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.656 ; gain = 157.816
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.582 ; gain = 157.168
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k160tifbg484-2L
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.656 ; gain = 157.816
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.582 ; gain = 157.168
|
||||
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 418.656 ; gain = 157.816
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-223] decloning instance 'SE1' (sign_extend_3bit) to 'SE3'
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 418.582 ; gain = 157.168
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-223] decloning instance 'CPU9bits0/SE1' (sign_extend_3bit) to 'CPU9bits0/SE3'
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
@@ -119,7 +124,6 @@ Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
4 Input 9 Bit Muxes := 5
|
||||
2 Input 9 Bit Muxes := 8
|
||||
2 Input 4 Bit Muxes := 2
|
||||
4 Input 4 Bit Muxes := 2
|
||||
16 Input 4 Bit Muxes := 1
|
||||
2 Input 3 Bit Muxes := 2
|
||||
@@ -135,11 +139,6 @@ Finished RTL Component Statistics
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module CPU9bits
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
4 Input 9 Bit Muxes := 1
|
||||
8 Input 2 Bit Muxes := 1
|
||||
Module dataMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
@@ -149,7 +148,6 @@ Detailed RTL Component Info :
|
||||
Module decoder
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 4 Bit Muxes := 1
|
||||
4 Input 4 Bit Muxes := 1
|
||||
Module register
|
||||
Detailed RTL Component Info :
|
||||
@@ -179,6 +177,11 @@ Module bit1_mux_2_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module CPU9bits
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
4 Input 9 Bit Muxes := 1
|
||||
8 Input 2 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
@@ -197,7 +200,7 @@ Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 586.449 ; gain = 325.035
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
@@ -208,22 +211,12 @@ ROM:
|
||||
|Module Name | RTL Object | Depth x Width | Implemented As |
|
||||
+------------------+------------+---------------+----------------+
|
||||
|instructionMemory | p_0_out | 64x9 | LUT |
|
||||
|CPU9bits | p_0_out | 64x9 | LUT |
|
||||
|CPU9bits_tb | p_0_out | 64x9 | LUT |
|
||||
+------------------+------------+---------------+----------------+
|
||||
|
||||
|
||||
Block RAM: Preliminary Mapping Report (see note below)
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|
||||
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6837] The timing for the instance i_0/dM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
@@ -235,21 +228,7 @@ No constraint files found.
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Block RAM: Final Mapping Report
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
Finished ROM, RAM, DSP and Shift Register Reporting
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 586.449 ; gain = 325.035
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -260,9 +239,8 @@ Report RTL Partitions:
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6837] The timing for the instance dM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 586.449 ; gain = 325.035
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -286,7 +264,7 @@ Start Final Netlist Cleanup
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
@@ -299,7 +277,7 @@ Report Check Netlist:
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -311,25 +289,25 @@ Report RTL Partitions:
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
@@ -342,63 +320,37 @@ Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+---------+------+
|
||||
| |Cell |Count |
|
||||
+------+---------+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |LUT2 | 13|
|
||||
|3 |LUT3 | 21|
|
||||
|4 |LUT4 | 23|
|
||||
|5 |LUT5 | 33|
|
||||
|6 |LUT6 | 135|
|
||||
|7 |MUXF7 | 11|
|
||||
|8 |RAMB18E1 | 1|
|
||||
|9 |FDRE | 81|
|
||||
|10 |IBUF | 2|
|
||||
|11 |OBUF | 10|
|
||||
+------+---------+------+
|
||||
+-+-----+------+
|
||||
| |Cell |Count |
|
||||
+-+-----+------+
|
||||
+-+-----+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-----------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-----------+------+
|
||||
|1 |top | | 331|
|
||||
|2 | Bank |RegFile | 45|
|
||||
|3 | r0 |register_5 | 15|
|
||||
|4 | r1 |register_6 | 9|
|
||||
|5 | r2 |register_7 | 11|
|
||||
|6 | r3 |register_8 | 10|
|
||||
|7 | FetchU |FetchUnit | 135|
|
||||
|8 | PC |register_4 | 135|
|
||||
|9 | RF |RegFile_0 | 137|
|
||||
|10 | r0 |register | 87|
|
||||
|11 | r1 |register_1 | 17|
|
||||
|12 | r2 |register_2 | 14|
|
||||
|13 | r3 |register_3 | 19|
|
||||
|14 | dM |dataMemory | 1|
|
||||
+------+---------+-----------+------+
|
||||
+------+---------+-------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-------+------+
|
||||
|1 |top | | 0|
|
||||
+------+---------+-------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 5 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 586.449 ; gain = 325.035
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 683.707 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 674.711 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
72 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
70 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 683.707 ; gain = 435.820
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 683.707 ; gain = 0.000
|
||||
synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 674.711 ; gain = 426.559
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 674.711 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Sat Apr 6 14:01:18 2019...
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_tb_utilization_synth.rpt -pb CPU9bits_tb_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Sat Apr 6 16:04:50 2019...
|
||||
BIN
lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.pb
Normal file
BIN
lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.pb
Normal file
Binary file not shown.
@@ -1,13 +1,13 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------------
|
||||
-----------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Sat Apr 6 14:01:18 2019
|
||||
| Date : Sat Apr 6 16:04:50 2019
|
||||
| Host : WM-G75VW running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
| Design : CPU9bits
|
||||
| Command : report_utilization -file CPU9bits_tb_utilization_synth.rpt -pb CPU9bits_tb_utilization_synth.pb
|
||||
| Design : CPU9bits_tb
|
||||
| Device : 7k160tifbg484-2L
|
||||
| Design State : Synthesized
|
||||
-----------------------------------------------------------------------------------------------------------
|
||||
| Design State : Fully Placed
|
||||
-----------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
@@ -15,14 +15,15 @@ Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
2. Slice Logic Distribution
|
||||
3. Memory
|
||||
4. DSP
|
||||
5. IO and GT Specific
|
||||
6. Clocking
|
||||
7. Specific Feature
|
||||
8. Primitives
|
||||
9. Black Boxes
|
||||
10. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
@@ -30,16 +31,15 @@ Table of Contents
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 193 | 0 | 101400 | 0.19 |
|
||||
| LUT as Logic | 193 | 0 | 101400 | 0.19 |
|
||||
| Slice LUTs | 0 | 0 | 101400 | 0.00 |
|
||||
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
|
||||
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
|
||||
| Slice Registers | 81 | 0 | 202800 | 0.04 |
|
||||
| Register as Flip Flop | 81 | 0 | 202800 | 0.04 |
|
||||
| Slice Registers | 0 | 0 | 202800 | 0.00 |
|
||||
| Register as Flip Flop | 0 | 0 | 202800 | 0.00 |
|
||||
| Register as Latch | 0 | 0 | 202800 | 0.00 |
|
||||
| F7 Muxes | 11 | 0 | 50700 | 0.02 |
|
||||
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
@@ -57,25 +57,45 @@ Table of Contents
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 81 | Yes | Reset | - |
|
||||
| 0 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
2. Slice Logic Distribution
|
||||
---------------------------
|
||||
|
||||
+------------------------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------------------------------------+------+-------+-----------+-------+
|
||||
| Slice | 0 | 0 | 25350 | 0.00 |
|
||||
| SLICEL | 0 | 0 | | |
|
||||
| SLICEM | 0 | 0 | | |
|
||||
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
|
||||
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
|
||||
| LUT as Distributed RAM | 0 | 0 | | |
|
||||
| LUT as Shift Register | 0 | 0 | | |
|
||||
| Slice Registers | 0 | 0 | 202800 | 0.00 |
|
||||
| Register driven from within the Slice | 0 | | | |
|
||||
| Register driven from outside the Slice | 0 | | | |
|
||||
| Unique Control Sets | 0 | | 25350 | 0.00 |
|
||||
+------------------------------------------+------+-------+-----------+-------+
|
||||
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
|
||||
|
||||
|
||||
3. Memory
|
||||
---------
|
||||
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0.5 | 0 | 325 | 0.15 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
|
||||
| RAMB18 | 1 | 0 | 650 | 0.15 |
|
||||
| RAMB18E1 only | 1 | | | |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 325 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 650 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
4. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
@@ -85,13 +105,13 @@ Table of Contents
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
5. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 12 | 0 | 285 | 4.21 |
|
||||
| Bonded IOB | 0 | 0 | 285 | 0.00 |
|
||||
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
|
||||
@@ -112,13 +132,13 @@ Table of Contents
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
6. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
@@ -128,7 +148,7 @@ Table of Contents
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
7. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
@@ -146,27 +166,15 @@ Table of Contents
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
8. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| LUT6 | 135 | LUT |
|
||||
| FDRE | 81 | Flop & Latch |
|
||||
| LUT5 | 33 | LUT |
|
||||
| LUT4 | 23 | LUT |
|
||||
| LUT3 | 21 | LUT |
|
||||
| LUT2 | 13 | LUT |
|
||||
| MUXF7 | 11 | MuxFx |
|
||||
| OBUF | 10 | IO |
|
||||
| IBUF | 2 | IO |
|
||||
| RAMB18E1 | 1 | Block Memory |
|
||||
| BUFG | 1 | Clock |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
9. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
@@ -174,8 +182,8 @@ Table of Contents
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
10. Instantiated Netlists
|
||||
-------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
Binary file not shown.
@@ -1,12 +1,14 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1554573635">
|
||||
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="CPU9bits_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="CPU9bits.vds"/>
|
||||
<File Type="RDS-DCP" Name="CPU9bits.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="CPU9bits_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="CPU9bits_timing_summary_synth.pb"/>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1554581051">
|
||||
<File Type="PA-TCL" Name="CPU9bits_tb.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="CPU9bits_tb_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="CPU9bits_tb_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="CPU9bits_tb.vds"/>
|
||||
<File Type="RDS-UTIL" Name="CPU9bits_tb_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="CPU9bits_tb_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="CPU9bits_tb.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="CPU9bits_tb_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="CPU9bits_tb_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
@@ -75,7 +77,7 @@
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="CPU9bits"/>
|
||||
<Option Name="TopModule" Val="CPU9bits_tb"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
|
||||
@@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log CPU9bits.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
|
||||
vivado -log CPU9bits_tb.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl
|
||||
|
||||
@@ -2,11 +2,11 @@
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Sat Apr 6 14:00:40 2019
|
||||
# Process ID: 8416
|
||||
# Start of session at: Sat Apr 6 16:04:16 2019
|
||||
# Process ID: 22928
|
||||
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
|
||||
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
|
||||
# Command line: vivado.exe -log CPU9bits_tb.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl
|
||||
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits_tb.vds
|
||||
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source CPU9bits.tcl -notrace
|
||||
source CPU9bits_tb.tcl -notrace
|
||||
|
||||
Binary file not shown.
Reference in New Issue
Block a user