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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

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WilliamMiceli
2019-04-06 14:19:45 -04:00
parent 2c2132fb9f f34b3d4098
commit e79e0cf74d
2 changed files with 34 additions and 2 deletions
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2
lab2CA.runs/synth_1/gen_run.xml
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@@ -4,8 +4,6 @@
<File Type="RDS-PROPCONSTRS" Name="CPU9bits_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
<File Type="RDS-RDS" Name="CPU9bits.vds"/>
<File Type="RDS-UTIL" Name="CPU9bits_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="CPU9bits_utilization_synth.pb"/>
<File Type="RDS-DCP" Name="CPU9bits.dcp"/>
<File Type="VDS-TIMINGSUMMARY" Name="CPU9bits_timing_summary_synth.rpt"/>
<File Type="VDS-TIMING-PB" Name="CPU9bits_timing_summary_synth.pb"/>

34
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -850,6 +850,40 @@ module register_tb();
end
endmodule
module fDPipReg(
input wire clk,
input wire reset,
input wire En,
input wire [42:0] Din,
output reg [42:0] Dout);
always @(posedge clk) begin
if (reset == 1'b1) begin
Dout <= 23'b0000;
end
else if (En == 1'b0) begin
Dout <= Din;
end
end
endmodule
module eMPipReg(
input wire clk,
input wire reset,
input wire En,
input wire [42:0] Din,
output reg [42:0] Dout);
always @(posedge clk) begin
if (reset == 1'b1) begin
Dout <= 23'b0000;
end
else if (En == 1'b0) begin
Dout <= Din;
end
end
endmodule
module shift_left(
input wire [7:0] A,
output wire [8:0] B);