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Added Pipeline

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Johannes
2019-04-06 17:51:44 -04:00
parent f34b3d4098
commit e6cb8e536b
70 changed files with 1721 additions and 1047 deletions
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lab2CA.runs/impl_1/CPU9bits.vdi
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@@ -2,29 +2,29 @@
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Mar 30 15:53:31 2019
# Process ID: 13696
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1
# Start of session at: Sat Apr 6 17:33:53 2019
# Process ID: 9496
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits.tcl -notrace
Command: link_design -top CPU9bits -part xc7k160tifbg484-2L
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Project 1-570] Preparing netlist for logic optimization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 581.816 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 577.664 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 587.391 ; gain = 332.746
link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:16 . Memory (MB): peak = 583.055 ; gain = 324.613
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
@@ -35,53 +35,53 @@ INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 603.059 ; gain = 15.668
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.719 . Memory (MB): peak = 595.676 ; gain = 12.621
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 257e1e38
Ending Cache Timing Information Task | Checksum: 178a9fcd1
Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1127.293 ; gain = 524.234
Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1128.926 ; gain = 533.250
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 257e1e38
Phase 1 Retarget | Checksum: 11e80142d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1225.961 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.086 . Memory (MB): peak = 1224.855 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 1 cells and removed 1 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 257e1e38
Phase 2 Constant propagation | Checksum: 11e80142d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 1225.961 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 1224.855 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 257e1e38
Phase 3 Sweep | Checksum: 11e80142d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.083 . Memory (MB): peak = 1225.961 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.098 . Memory (MB): peak = 1224.855 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 257e1e38
Phase 4 BUFG optimization | Checksum: 11e80142d
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.093 . Memory (MB): peak = 1225.961 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.103 . Memory (MB): peak = 1224.855 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 257e1e38
Phase 5 Shift Register Optimization | Checksum: 8b9eda27
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.196 . Memory (MB): peak = 1225.961 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.145 . Memory (MB): peak = 1224.855 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 257e1e38
Phase 6 Post Processing Netlist | Checksum: 8b9eda27
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.199 . Memory (MB): peak = 1225.961 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.147 . Memory (MB): peak = 1224.855 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
@@ -90,7 +90,7 @@ Opt_design Change Summary
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 0 | 0 |
| Retarget | 1 | 1 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 0 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
@@ -102,10 +102,10 @@ Opt_design Change Summary
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1225.961 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 257e1e38
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1224.855 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 8b9eda27
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.206 . Memory (MB): peak = 1225.961 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.150 . Memory (MB): peak = 1224.855 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
@@ -124,40 +124,39 @@ Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 1 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 2
Ending PowerOpt Patch Enables Task | Checksum: 257e1e38
Ending PowerOpt Patch Enables Task | Checksum: 8b9eda27
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1335.719 ; gain = 0.000
Ending Power Optimization Task | Checksum: 257e1e38
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1334.406 ; gain = 0.000
Ending Power Optimization Task | Checksum: 8b9eda27
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1335.719 ; gain = 109.758
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.786 . Memory (MB): peak = 1334.406 ; gain = 109.551
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 257e1e38
Ending Final Cleanup Task | Checksum: 8b9eda27
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1335.719 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 257e1e38
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 8b9eda27
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
28 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1335.719 ; gain = 748.328
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000
opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1334.406 ; gain = 751.352
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated.
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
Command: report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt.
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
@@ -175,128 +174,127 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e0025bd
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 44f3ef01
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1335.719 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1334.406 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: be8e8081
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b481c8c5
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 154227d99
Phase 1.3 Build Placer Netlist Model | Checksum: 16bafe571
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 154227d99
Phase 1.4 Constrain Clocks/Macros | Checksum: 16bafe571
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 154227d99
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 16bafe571
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 154227d99
Phase 2.1 Floorplanning | Checksum: 16bafe571
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1334.406 ; gain = 0.000
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
Phase 2 Global Placement | Checksum: 168f30526
Phase 2 Global Placement | Checksum: 187ab5e99
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 168f30526
Phase 3.1 Commit Multi Column Macros | Checksum: 187ab5e99
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 10b26ca05
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 168760e64
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 171e1f517
Phase 3.3 Area Swap Optimization | Checksum: 105becb87
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 171e1f517
Phase 3.4 Pipeline Register Optimization | Checksum: 105becb87
Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: eb242549
Phase 3.5 Small Shape Detail Placement | Checksum: cd32f4e6
Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: eb242549
Phase 3.6 Re-assign LUT pins | Checksum: cd32f4e6
Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: eb242549
Phase 3.7 Pipeline Register Optimization | Checksum: cd32f4e6
Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 3 Detail Placement | Checksum: eb242549
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 3 Detail Placement | Checksum: cd32f4e6
Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: eb242549
Phase 4.1 Post Commit Optimization | Checksum: cd32f4e6
Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: eb242549
Phase 4.2 Post Placement Cleanup | Checksum: cd32f4e6
Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: eb242549
Phase 4.3 Placer Reporting | Checksum: cd32f4e6
Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: eb242549
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 18c80bbbe
Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up | Checksum: eb242549
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18c80bbbe
Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Ending Placer Task | Checksum: 99ceed10
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
Ending Placer Task | Checksum: 101790dce
Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
45 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1335.719 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.323 . Memory (MB): peak = 1335.719 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 1334.406 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file CPU9bits_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.130 . Memory (MB): peak = 1335.719 ; gain = 0.000
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1334.406 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1335.719 ; gain = 0.000
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1334.406 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
@@ -308,68 +306,68 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 7bcec753 ConstDB: 0 ShapeSum: 1e0025bd RouteDB: 0
Checksum: PlaceDB: 2e37d8f5 ConstDB: 0 ShapeSum: d34134d9 RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 16c615449
Phase 1 Build RT Design | Checksum: 7ebb6ebf
Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1486.191 ; gain = 150.473
Post Restoration Checksum: NetGraph: 8cbcc684 NumContArr: dfa48dc5 Constraints: 0 Timing: 0
Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 1485.609 ; gain = 151.203
Post Restoration Checksum: NetGraph: 10180109 NumContArr: 6ea36db6 Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 16c615449
Phase 2.1 Fix Topology Constraints | Checksum: 7ebb6ebf
Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1490.352 ; gain = 154.633
Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 1489.359 ; gain = 154.953
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 16c615449
Phase 2.2 Pre Route Cleanup | Checksum: 7ebb6ebf
Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1490.352 ; gain = 154.633
Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 1489.359 ; gain = 154.953
Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: 10053be5d
Phase 2 Router Initialization | Checksum: dbaddab7
Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1517.723 ; gain = 182.004
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 94ab7af4
Phase 3 Initial Routing | Checksum: ad0f318a
Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 15
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: ab64b9a3
Phase 4.1 Global Iteration 0 | Checksum: 1246629fb
Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Phase 4 Rip-up And Reroute | Checksum: ab64b9a3
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 4 Rip-up And Reroute | Checksum: 1246629fb
Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: ab64b9a3
Phase 5 Delay and Skew Optimization | Checksum: 1246629fb
Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: ab64b9a3
Phase 6.1 Hold Fix Iter | Checksum: 1246629fb
Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Phase 6 Post Hold Fix | Checksum: ab64b9a3
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 6 Post Hold Fix | Checksum: 1246629fb
Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.00626714 %
Global Horizontal Routing Utilization = 0.0102302 %
Global Vertical Routing Utilization = 0.00477869 %
Global Horizontal Routing Utilization = 0.00797101 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
@@ -379,10 +377,10 @@ Router Utilization Summary
Number of Node Overlaps = 0
Congestion Report
North Dir 1x1 Area, Max Cong = 18.9189%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 10.8108%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 22.0588%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 27.9412%, No Congested Regions.
North Dir 1x1 Area, Max Cong = 9.00901%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 13.5135%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 16.1765%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 14.7059%, No Congested Regions.
------------------------------
Reporting congestion hotspots
@@ -404,50 +402,50 @@ Direction: West
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: ab64b9a3
Phase 7 Route finalize | Checksum: 1246629fb
Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: ab64b9a3
Phase 8 Verifying routed nets | Checksum: 1246629fb
Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 148b7f565
Phase 9 Depositing Routes | Checksum: 1219f5402
Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004
Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
57 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:56 ; elapsed = 00:00:42 . Memory (MB): peak = 1517.723 ; gain = 182.004
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1517.723 ; gain = 0.000
route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1516.082 ; gain = 181.676
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1516.082 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1517.723 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.062 . Memory (MB): peak = 1516.082 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
Command: report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt.
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
Command: report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt.
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
Command: report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
@@ -470,4 +468,4 @@ INFO: [runtcl-4] Executing : report_clock_utilization -file CPU9bits_clock_utili
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Sat Mar 30 15:55:20 2019...
INFO: [Common 17-206] Exiting Vivado at Sat Apr 6 17:35:04 2019...