William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Added Pipeline

Browse Source
This commit is contained in:
Johannes
2019-04-06 17:51:44 -04:00
parent f34b3d4098
commit e6cb8e536b
70 changed files with 1721 additions and 1047 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt
View File

@@ -1,8 +1,8 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Mar 30 15:55:20 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Date : Sat Apr 6 17:35:04 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
| Design : CPU9bits
| Device : 7k160ti-fbg484
@@ -52,7 +52,7 @@ Table of Contents
1. checking no_clock
--------------------
There are 22 register/latch pins with no clock driven by root clock pin: clk (HIGH)
There are 59 register/latch pins with no clock driven by root clock pin: clk (HIGH)
2. checking constant_clock
@@ -67,7 +67,7 @@ Table of Contents
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 75 pins that are not constrained for maximum delay. (HIGH)
There are 152 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.