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Johannes
2019-04-06 17:51:44 -04:00
parent f34b3d4098
commit e6cb8e536b
70 changed files with 1721 additions and 1047 deletions
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lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt
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@@ -1,8 +1,8 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Mar 30 15:54:32 2019
| Host : WM-G75VW running 64-bit major release (build 9200)
| Date : Sat Apr 6 17:34:31 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
| Design : CPU9bits
| Device : 7k160tifbg484-2L
@@ -31,11 +31,11 @@ Table of Contents
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs | 73 | 0 | 101400 | 0.07 |
| LUT as Logic | 73 | 0 | 101400 | 0.07 |
| Slice LUTs | 54 | 0 | 101400 | 0.05 |
| LUT as Logic | 54 | 0 | 101400 | 0.05 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 21 | 0 | 202800 | 0.01 |
| Register as Flip Flop | 21 | 0 | 202800 | 0.01 |
| Slice Registers | 58 | 0 | 202800 | 0.03 |
| Register as Flip Flop | 58 | 0 | 202800 | 0.03 |
| Register as Latch | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
@@ -57,7 +57,7 @@ Table of Contents
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 21 | Yes | Reset | - |
| 58 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -68,20 +68,20 @@ Table of Contents
| Site Type | Used | Fixed | Available | Util% |
+--------------------------------------------+------+-------+-----------+-------+
| Slice | 21 | 0 | 25350 | 0.08 |
| SLICEL | 11 | 0 | | |
| SLICEM | 10 | 0 | | |
| LUT as Logic | 73 | 0 | 101400 | 0.07 |
| SLICEL | 12 | 0 | | |
| SLICEM | 9 | 0 | | |
| LUT as Logic | 54 | 0 | 101400 | 0.05 |
| using O5 output only | 0 | | | |
| using O6 output only | 65 | | | |
| using O5 and O6 | 8 | | | |
| using O6 output only | 40 | | | |
| using O5 and O6 | 14 | | | |
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 21 | 0 | 202800 | 0.01 |
| Register driven from within the Slice | 4 | | | |
| Register driven from outside the Slice | 17 | | | |
| LUT in front of the register is unused | 0 | | | |
| LUT in front of the register is used | 17 | | | |
| Slice Registers | 58 | 0 | 202800 | 0.03 |
| Register driven from within the Slice | 34 | | | |
| Register driven from outside the Slice | 24 | | | |
| LUT in front of the register is unused | 17 | | | |
| LUT in front of the register is used | 7 | | | |
| Unique Control Sets | 3 | | 25350 | 0.01 |
+--------------------------------------------+------+-------+-----------+-------+
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
@@ -180,15 +180,16 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT6 | 37 | LUT |
| LUT4 | 27 | LUT |
| FDRE | 21 | Flop & Latch |
| FDRE | 58 | Flop & Latch |
| LUT4 | 23 | LUT |
| LUT3 | 18 | LUT |
| LUT5 | 11 | LUT |
| OBUF | 10 | IO |
| LUT5 | 10 | LUT |
| LUT2 | 4 | LUT |
| LUT3 | 3 | LUT |
| LUT6 | 9 | LUT |
| LUT2 | 6 | LUT |
| IBUF | 2 | IO |
| RAMB18E1 | 1 | Block Memory |
| LUT1 | 1 | LUT |
| BUFG | 1 | Clock |
+----------+------+---------------------+