William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Added Pipeline

Browse Source
This commit is contained in:
Johannes
2019-04-06 17:51:44 -04:00
parent f34b3d4098
commit e6cb8e536b
70 changed files with 1721 additions and 1047 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
lab2CA.sim/sim_1/behav/xsim/CPU9bits_vlog.prj Normal file
View File

@@ -0,0 +1,19 @@
# compile verilog/system verilog design source files
verilog xil_defaultlib \
"../../../../lab2CA.srcs/sources_1/new/ALU.v" \
"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
"../../../../lab2CA.srcs/sources_1/new/ControlUnit.v" \
"../../../../lab2CA.srcs/sources_1/new/EMModule.v" \
"../../../../lab2CA.srcs/sources_1/new/FDModule.v" \
"../../../../lab2CA.srcs/sources_1/new/FetchUnit.v" \
"../../../../lab2CA.srcs/sources_1/new/RegFile.v" \
"../../../../lab2CA.srcs/sources_1/new/WMUdule.v" \
"../../../../lab2CA.srcs/sources_1/new/dataMemory.v" \
"../../../../lab2CA.srcs/sources_1/new/instructionMemory.v" \
"../../../../lab2CA.srcs/sources_1/new/CPU9bits.v" \
# compile glbl module
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort