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Added Pipeline

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Johannes
2019-04-06 17:51:44 -04:00
parent f34b3d4098
commit e6cb8e536b
70 changed files with 1721 additions and 1047 deletions
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33
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -260,16 +260,23 @@ endmodule
module decoder (
input wire [1:0] index,
input wire En,
output reg [3:0] regOut);
always @ (index)
case(index)
2'b00: regOut <= 4'b1110;
2'b01: regOut <= 4'b1101;
2'b10: regOut <= 4'b1011;
2'b11: regOut <= 4'b0111;
default: regOut <= 4'b1111;
endcase
if (En == 0) begin
case(index)
2'b00: regOut <= 4'b1110;
2'b01: regOut <= 4'b1101;
2'b10: regOut <= 4'b1011;
2'b11: regOut <= 4'b0111;
default: regOut <= 4'b1111;
endcase
end
else begin
regOut <= 4'b1111;
end
endmodule
//testbench
@@ -843,12 +850,12 @@ module fDPipReg(
input wire clk,
input wire reset,
input wire En,
input wire [42:0] Din,
output reg [42:0] Dout);
input wire [50:0] Din,
output reg [50:0] Dout);
always @(posedge clk) begin
if (reset == 1'b1) begin
Dout <= 23'b0000;
Dout <= 50'b00000000000000000000000000000000000000000000000000;
end
else if (En == 1'b0) begin
Dout <= Din;
@@ -860,12 +867,12 @@ module eMPipReg(
input wire clk,
input wire reset,
input wire En,
input wire [42:0] Din,
output reg [42:0] Dout);
input wire [61:0] Din,
output reg [61:0] Dout);
always @(posedge clk) begin
if (reset == 1'b1) begin
Dout <= 23'b0000;
Dout <= 60'b0000000000000000000000000000000000000000000000000000000000000000000000;
end
else if (En == 1'b0) begin
Dout <= Din;