Added Pipeline

2019-04-06 17:51:44 -04:00
parent f34b3d4098
commit e6cb8e536b
70 changed files with 1721 additions and 1047 deletions
--- a/lab2CA.srcs/sources_1/new/FDModule.v
+++ b/lab2CA.srcs/sources_1/new/FDModule.v
@@ -0,0 +1,60 @@
+`timescale 1ns / 1ps
+
+module FDModule(
+        input wire reset, clk, FUIdx, En,
+        input wire [8:0] RFIn, AddrIn, 
+        input wire[1:0] RFIdx,
+        output wire [50:0] result,
+        output wire done
+        );
+        
+        
+        wire [8:0] instr, op1, op0, PCout;
+        wire [3:0] aluOp;
+        wire [2:0] FU;
+        wire [1:0] bankS;
+        wire addiS, RegEn, loadS, halt, link, js, dataMemEn;
+       
+        assign result = {instr,op0,op1,PCout,addiS,RegEn,loadS,link,js,dataMemEn,aluOp,FU,bankS};   // concat all signals into one
+
+        
+    instructionMemory iM(
+        .address(PCout),
+        .readData(instr)
+    );
+    
+    FetchUnit FetchU(
+        .clk(clk),
+        .reset(reset),
+        .op_idx(FUIdx),
+        .AddrIn(AddrIn),
+        .AddrOut(PCout)
+    );
+    
+    RegFile RF(
+        .clk(clk),
+        .reset(reset),
+        .write_index(RFIdx),
+        .op0_idx(instr[4:3]),
+        .op1_idx(instr[2:1]),
+        .write_data(RFIn),
+        .op0(op0),
+        .op1(op1),
+        .En(En)
+    );    
+    
+        ControlUnit CU(
+        .instIn(instr[8:5]),
+        .functBit(instr[0]),
+        .aluOut(aluOp),
+        .FU(FU),
+        .addi(addiS),
+        .mem(loadS),
+        .dataMemEn(dataMemEn),
+        .RegEn(RegEn),
+        .halt(done),
+        .link(link),
+        .bank(bankS),
+        .js(js)
+    );
+endmodule