Added Pipeline

lab2CA.srcs/sources_1/new/RegFile.v

@@ -1,6 +1,6 @@
 `timescale 1ns / 1ps
 
-module RegFile(input wire clk, reset,
+module RegFile(input wire clk, reset,En,
                 input wire [1:0] write_index, op0_idx, op1_idx,
                 input wire [8:0] write_data,
                 output wire [8:0] op0, op1);
@@ -12,7 +12,8 @@ module RegFile(input wire clk, reset,
     
     decoder d0(
         .index(write_index),
-        .regOut(decOut)
+        .regOut(decOut),
+        .En(En)
     );