William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Added Pipeline

Browse Source
This commit is contained in:
Johannes
2019-04-06 17:51:44 -04:00
parent f34b3d4098
commit e6cb8e536b
70 changed files with 1721 additions and 1047 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
lab2CA.xpr
View File

@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="39" Path="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr">
<Project Version="7" Minor="39" Path="C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="0a5803efda44405bb28bbf43ba22e808"/>
@@ -31,7 +31,7 @@
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="343"/>
<Option Name="WTXSimLaunchSim" Val="360"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -80,6 +80,20 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/EMModule.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/FDModule.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/FetchUnit.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -94,6 +108,13 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/WMUdule.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/dataMemory.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -148,7 +169,7 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="CPU9bits"/>
<Option Name="TopModule" Val="CPU9bits_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>