Result output of CPU pretty much implemented; not yet tested

2019-03-29 18:16:45 -04:00
parent acf7f9e92b
commit ea0111542a
2 changed files with 9 additions and 13 deletions
--- a/lab2CA.srcs/sources_1/new/CPU9bits.v
+++ b/lab2CA.srcs/sources_1/new/CPU9bits.v
@@ -180,16 +180,12 @@ module CPU9bits(
        case(instr[8:5])
        4'b0001: // Load Byte
            result <= dataMemOut;
-        4'b0011: // Link
-            result <= linkData;
        4'b0101: // Add/Subtract
            result <= AluOut;
        4'b0110: // Add Immediate
            result <= AddiOut;
        4'b0111: // Set if Less Than
            result <= AluOut;
-        4'b1010: // Bank Load/Bank Store
-            result <= RFIn;
        4'b1101: // NOR
            result <= AluOut;
        4'b1110: // OR/AND