5 Commits

Author	SHA1	Message	Date
Johannes	3f01492398	Added SLT ... There is a testbench but when I try to run it on my computer it brings up some regFile simulation even though SLT is set to top. Not sure if its my pc or the code	2019-03-12 19:49:46 -04:00
goochey	c047c801aa	Lots of changes ... Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.	2019-02-27 12:06:17 -05:00
WilliamMiceli	6900e74405	Miscellaneous	2019-02-21 15:09:00 -05:00
goochey	54cccd419f	Lots ... Lots	2019-02-16 17:40:18 -05:00
goochey	faf9f883dd	Collaborative - Fixes and Testbenches for Basic Modules so far	2019-02-16 16:29:12 -05:00