William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
Files
27f6d24b8894f0a2054c952ed46b323981d5e9f8
WMU-ECE-3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir
History
jose.rodriguezlabra 27f6d24b88 Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2 
# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.runs/impl_1/gen_run.xml
#	lab2CA.runs/synth_1/gen_run.xml
#	lab2CA.sim/sim_1/behav/xsim/xelab.pb
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.sim/sim_1/behav/xsim/xvlog.pb
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
2019-03-24 14:17:59 -04:00
..
add1bit_tb_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
add9bit_tb_behav
Many Changes
2019-03-12 21:14:27 -04:00
ALU_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
alu_tb_behav
fetch unit test
2019-02-20 11:31:25 -05:00
and1bit_tb_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
and9bit_tb_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
comparator_tb_behav
Computer works (kinda)
2019-03-13 12:51:44 -04:00
CPU9bits_tb_behav
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
2019-03-24 14:17:59 -04:00
dataMemory_tb_behav
Tested zero
2019-03-16 14:55:11 -04:00
decoder_tb_behav
Lots of changes
2019-02-27 12:06:17 -05:00
fetchUnit_tb_behav
Miscellaneous
2019-02-21 15:09:00 -05:00
instructionMemory_tb_behav
Instruction & Data Memory
2019-03-16 14:16:02 -04:00
mux_2_1_tb_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
mux_4_1_tb_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
mux_8_1_tb_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
nor_1bit_tb_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
nor_9bit_tb_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
not_1bit_tb_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
not_9bit_tb_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
or_1bit_tb_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
or_9bit_tb_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
regFile_tb_behav
Lots of changes
2019-02-27 12:06:17 -05:00
register_tb_behav
fetch unit test
2019-02-20 11:31:25 -05:00
shift_logical_left_tb_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
shift_logical_right_tb_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
slt_tb_behav
Many Changes
2019-03-12 21:14:27 -04:00
sub_9bit_tb_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
twos_compliment_tb_behav
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00