3f01492398
There is a testbench but when I try to run it on my computer it brings up some regFile simulation even though SLT is set to top. Not sure if its my pc or the code
1041 lines
18 KiB
Verilog
1041 lines
18 KiB
Verilog
`timescale 1ns / 1ps
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module add_1bit(
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input wire A,
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input wire B,
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input wire Cin,
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output wire S,
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output wire Cout);
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assign S = (A ^ B) ^ Cin;
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assign Cout = ((A ^ B) & Cin) | (A & B);
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endmodule
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//testbench
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module add1bit_tb();
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reg v;
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reg w;
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reg x;
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wire y;
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wire z;
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add_1bit tb0(
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.A(v),
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.B(w),
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.Cin(x),
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.S(y),
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.Cout(z));
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initial begin
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v = 0;
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w = 0;
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x = 0;
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#5
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v = 0;
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w = 1;
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x = 0;
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#5
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v = 0;
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w = 0;
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x = 1;
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#5
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v = 1;
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w = 1;
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x = 0;
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#5
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v = 1;
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w = 1;
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x = 1;
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#5
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$finish;
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end
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endmodule
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module add_9bit(
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input wire [8:0] A,
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input wire [8:0] B,
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input wire Cin,
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output wire [8:0] Sum,
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output wire Cout);
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wire C_add0;
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wire C_add1;
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wire C_add2;
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wire C_add3;
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wire C_add4;
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wire C_add5;
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wire C_add6;
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wire C_add7;
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add_1bit add0(
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.A(A[0]),
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.B(B[0]),
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.Cin(Cin),
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.S(Sum[0]),
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.Cout(C_add0));
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add_1bit add1(
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.A(A[1]),
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.B(B[1]),
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.Cin(C_add0),
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.S(Sum[1]),
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.Cout(C_add1));
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add_1bit add2(
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.A(A[2]),
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.B(B[2]),
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.Cin(C_add1),
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.S(Sum[2]),
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.Cout(C_add2));
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add_1bit add3(
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.A(A[3]),
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.B(B[3]),
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.Cin(C_add2),
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.S(Sum[3]),
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.Cout(C_add3));
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add_1bit add4(
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.A(A[4]),
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.B(B[4]),
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.Cin(C_add3),
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.S(Sum[4]),
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.Cout(C_add4));
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add_1bit add5(
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.A(A[5]),
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.B(B[5]),
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.Cin(C_add4),
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.S(Sum[5]),
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.Cout(C_add5));
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add_1bit add6(
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.A(A[6]),
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.B(B[6]),
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.Cin(C_add5),
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.S(Sum[6]),
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.Cout(C_add6));
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add_1bit add7(
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.A(A[7]),
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.B(B[7]),
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.Cin(C_add6),
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.S(Sum[7]),
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.Cout(C_add7));
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add_1bit add8(
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.A(A[8]),
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.B(B[8]),
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.Cin(C_add7),
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.S(Sum[8]),
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.Cout(Cout));
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endmodule
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//testbench
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module add9bit_tb();
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reg [8:0] a,b;
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reg cin;
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wire [8:0] s;
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wire cout;
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add_9bit tb0(
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.A(a),
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.B(b),
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.Cin(cin),
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.Sum(s),
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.Cout(cout));
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initial begin
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a = 9'b000000000;
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b = 9'b000000000;
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cin = 0;
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#5
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a = 9'b000000001;
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b = 9'b000000000;
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cin = 0;
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#5
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a = 9'b000000000;
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b = 9'b000000001;
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cin = 1;
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#5
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a = 9'b000000001;
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b = 9'b000000001;
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cin = 0;
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#5
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a = 9'b000001000;
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b = 9'b000000001;
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cin = 1;
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end
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endmodule
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module and_9bit(
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input wire [8:0] A,
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input wire [8:0] B,
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output wire [8:0] C);
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assign C = A & B;
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endmodule
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//testbench
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module and9bit_tb();
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reg [8:0] a,b;
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wire [8:0] c;
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and_9bit and0(
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.A(a),
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.B(b),
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.C(c));
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initial begin
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a = 9'b000000000;
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b = 9'b000000000;
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#5
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a = 9'b000000000;
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b = 9'b000000001;
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#5
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a = 9'b000000001;
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b = 9'b000000000;
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#5
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a = 9'b000000001;
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b = 9'b000000001;
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#5
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a = 9'b000100001;
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b = 9'b000000001;
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#5
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a = 9'b000100001;
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b = 9'b000100001;
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#5
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$finish;
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end
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endmodule
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module decoder (
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input wire en,
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input wire [1:0] index,
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output reg [3:0] regOut);
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always @(en, index)begin
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if(en == 1)begin
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case(index)
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2'b00: regOut <= 4'b0001;
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2'b01: regOut <= 4'b0010;
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2'b10: regOut <= 4'b0100;
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2'b11: regOut <= 4'b1000;
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default: regOut <= 4'bxxxx;
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endcase
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end
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end
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endmodule
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//testbench
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module decoder_tb();
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reg enable;
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reg [1:0] indexIn;
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wire [3:0] regOut;
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decoder dec0(
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.en(enable),
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.index(indexIn),
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.regOut(regOut));
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initial begin
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enable = 0;
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indexIn = 2'b00;
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#5
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enable = 1;
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#5
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indexIn = 2'b01;
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#5
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indexIn = 2'b10;
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#5
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indexIn = 2'b11;
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#5
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$finish;
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end
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endmodule
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module gen_clock();
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reg clk;
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initial begin
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clk = 1'b0;
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end
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always begin
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#5 clk = ~clk; // Period to be determined
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end
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endmodule
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module mux_2_1(
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input wire switch,
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input wire [8:0] A,B,
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output reg [8:0] out);
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always @(A,B,switch) begin
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case (switch)
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1'b0 : out = A;
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1'b1 : out = B;
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default : out = 9'bxxxxxxxxx;
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endcase
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end
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endmodule
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//testbench
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module mux_2_1_tb();
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reg s;
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reg [8:0] a,b;
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wire [8:0] c;
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mux_2_1 tb0(
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.switch(s),
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.A(a),
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.B(b),
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.out(c));
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initial begin
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s = 0;
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a = 9'b000000101;
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b = 9'b000000000;
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#5
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s = 1;
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a = 9'b000000001;
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b = 9'b000100001;
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#5
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s = 0;
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a = 9'b000000000;
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b = 9'b000000001;
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#5
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s = 1;
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a = 9'b000000001;
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b = 9'b000000001;
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#5
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s = 0;
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a = 9'b000010001;
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b = 9'b000000001;
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#5
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s = 1;
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a = 9'b000010001;
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b = 9'b000010111;
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#5
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$finish;
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end
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endmodule
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module mux_4_1(input wire [1:0] switch,
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input wire [8:0] A,B,C,D,
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output reg [8:0] out);
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always @(A,B,C,D,switch) begin
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case (switch)
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2'b00 : out = A;
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2'b01 : out = B;
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2'b10 : out = C;
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2'b11 : out = D;
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default : out = 9'bxxxxxxxxx;
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endcase
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end
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endmodule
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//testbench
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module mux_4_1_tb();
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reg [1:0] s;
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reg [8:0] a,b,c,d;
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wire [8:0] e;
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mux_4_1 tb0(
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.switch(s),
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.A(a),
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.B(b),
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.C(c),
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.D(d),
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.out(e));
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initial begin
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s = 2'b00;
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a = 9'b000000101;
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b = 9'b000111100;
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c = 9'b001001001;
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d = 9'b100000000;
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#5
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s = 2'b01;
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a = 9'b000000101;
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b = 9'b000111100;
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c = 9'b001001001;
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d = 9'b100000000;
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#5
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s = 2'b10;
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a = 9'b000000101;
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b = 9'b000111100;
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c = 9'b001001001;
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d = 9'b100000000;
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#5
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s = 2'b11;
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a = 9'b000000101;
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b = 9'b000111100;
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c = 9'b001001001;
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d = 9'b100000000;
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#5
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$finish;
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end
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endmodule
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module mux_8_1(
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input wire [2:0] switch,
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input wire [8:0] A,B,C,D,E,F,G,H,
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output reg [8:0] out);
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always @(A,B,C,D,E,F,G,H,switch) begin
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case (switch)
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3'b000 : out = A;
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3'b001 : out = B;
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3'b010 : out = C;
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3'b011 : out = D;
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3'b100 : out = E;
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3'b101 : out = F;
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3'b110 : out = G;
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3'b111 : out = H;
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default : out = 9'bxxxxxxxxx;
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endcase
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end
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endmodule
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//testbench
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module mux_8_1_tb();
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reg [2:0] s;
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reg [8:0] a,b,c,d,e,f,g,h;
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wire [8:0] out;
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mux_8_1 tb0(
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.switch(s),
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.A(a),
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.B(b),
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.C(c),
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.D(d),
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.E(e),
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.F(f),
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.G(g),
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.H(h),
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.out(out));
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initial begin
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s = 3'b000;
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a = 9'b000000101;
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b = 9'b000111100;
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c = 9'b001001001;
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d = 9'b100110000;
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e = 9'b010000101;
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f = 9'b010111100;
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g = 9'b011001001;
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h = 9'b111000000;
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#5
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s = 3'b001;
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#5
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s = 3'b010;
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#5
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s = 3'b011;
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#5
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s = 3'b100;
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#5
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s = 3'b101;
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#5
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s = 3'b110;
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#5
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s = 3'b111;
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#5
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$finish;
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end
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endmodule
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module mux_16_1(
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input wire [3:0] switch,
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input wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,
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output reg [8:0] out);
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always @(A,B,C,D,E,F,G,H,switch) begin
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case (switch)
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4'b0000 : out = A;
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4'b0001 : out = B;
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4'b0010 : out = C;
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4'b0011 : out = D;
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4'b0100 : out = E;
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4'b0101 : out = F;
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4'b0110 : out = G;
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4'b0111 : out = H;
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4'b1000 : out = I;
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4'b1001 : out = J;
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4'b1010 : out = K;
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4'b1011 : out = L;
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4'b1100 : out = M;
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4'b1101 : out = N;
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4'b1110 : out = O;
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4'b1111 : out = P;
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default : out = 9'bxxxxxxxxx;
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endcase
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end
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endmodule
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|
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//testbench
|
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module mux_16_1_tb();
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reg [2:0] switch;
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reg [8:0] a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p;
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wire [8:0] out;
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mux_16_1 tb0(
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.switch(switch),
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.A(a),
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.B(b),
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.C(c),
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.D(d),
|
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.E(e),
|
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.F(f),
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.G(g),
|
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.H(h),
|
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.I(i),
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.J(j),
|
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.K(k),
|
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.L(l),
|
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.M(m),
|
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.N(n),
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.O(o),
|
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.P(p),
|
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.out(out));
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|
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initial begin
|
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switch = 4'b0000;
|
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a = 9'b000000101;
|
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b = 9'b000111100;
|
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c = 9'b001001001;
|
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d = 9'b100110000;
|
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e = 9'b010000101;
|
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f = 9'b010111100;
|
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g = 9'b011001001;
|
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h = 9'b111000000;
|
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i = 9'b100100101;
|
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j = 9'b000001100;
|
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k = 9'b001001001;
|
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l = 9'b100110011;
|
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m = 9'b010111101;
|
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n = 9'b010110100;
|
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o = 9'b100101001;
|
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p = 9'b111001100;
|
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#5
|
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switch = 4'b0001;
|
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#5
|
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switch = 4'b0010;
|
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#5
|
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switch = 4'b0011;
|
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#5
|
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switch = 4'b0100;
|
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#5
|
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switch = 4'b0101;
|
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#5
|
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switch = 4'b0110;
|
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#5
|
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switch = 4'b0111;
|
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#5
|
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switch = 4'b1000;
|
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#5
|
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switch = 4'b1001;
|
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#5
|
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switch = 4'b1010;
|
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#5
|
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switch = 4'b1011;
|
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#5
|
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switch = 4'b1100;
|
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#5
|
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switch = 4'b1101;
|
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#5
|
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switch = 4'b1110;
|
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#5
|
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switch = 4'b1111;
|
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#5
|
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$finish;
|
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|
|
end
|
|
endmodule
|
|
|
|
module nor_9bit(
|
|
input wire [8:0] A,
|
|
input wire [8:0] B,
|
|
output wire [8:0] C);
|
|
|
|
assign C = ~(A | B);
|
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|
|
endmodule
|
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|
|
//testbench
|
|
module nor_9bit_tb();
|
|
reg [8:0] a;
|
|
reg [8:0] b;
|
|
wire [8:0] c;
|
|
|
|
nor_9bit nor0(
|
|
.A(a),
|
|
.B(b),
|
|
.C(c));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
b = 9'b000000000;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b000000001;
|
|
#5
|
|
a = 9'b000000001;
|
|
b = 9'b000000000;
|
|
#5
|
|
a = 9'b000000001;
|
|
b = 9'b000000001;
|
|
#5
|
|
a = 9'b000100001;
|
|
b = 9'b000000001;
|
|
#5
|
|
a = 9'b000100001;
|
|
b = 9'b000100001;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module not_9bit(
|
|
input wire [8:0] A,
|
|
output wire [8:0] B);
|
|
|
|
assign B = ~A;
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module not_9bit_tb();
|
|
reg [8:0] a;
|
|
wire [8:0] b;
|
|
|
|
not_9bit not0(
|
|
.A(a),
|
|
.B(b));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
#5
|
|
a = 9'b000000001;
|
|
#5
|
|
a = 9'b000111000;
|
|
#5
|
|
a = 9'b010101010;
|
|
#5
|
|
a = 9'b101010101;
|
|
#5
|
|
a = 9'b111111111;
|
|
#5
|
|
a = 9'b100000001;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module or_9bit(
|
|
input wire [8:0] A,
|
|
input wire [8:0] B,
|
|
output wire [8:0] C);
|
|
|
|
assign C = A | B;
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module or_9bit_tb();
|
|
reg [8:0] a;
|
|
reg [8:0] b;
|
|
wire [8:0] c;
|
|
|
|
or_9bit tb0(
|
|
.A(a),
|
|
.B(b),
|
|
.C(c));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
b = 9'b000000000;
|
|
#5
|
|
a = 9'b111111111;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b111111111;
|
|
b = 9'b000000000;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b010101010;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b010101010;
|
|
b = 9'b101010101;
|
|
#5
|
|
a = 9'b000011111;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b000010000;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module register(
|
|
input wire clk, reset,
|
|
input wire En,
|
|
input wire [8:0] Din,
|
|
output reg [8:0] Dout);
|
|
|
|
always @(posedge clk) begin
|
|
if (reset == 1'b1) begin
|
|
Dout = 9'b000000000;
|
|
end
|
|
else if (En == 1'b0) begin
|
|
Dout = Din;
|
|
end
|
|
else begin
|
|
Dout = Dout;
|
|
end
|
|
end
|
|
endmodule
|
|
|
|
//testbench
|
|
module register_tb();
|
|
reg clk,reset;
|
|
reg [1:0] En;
|
|
reg [8:0] Din;
|
|
wire [8:0] Dout;
|
|
|
|
register tb0(
|
|
.clk(clk),
|
|
.reset(reset),
|
|
.En(En),
|
|
.Din(Din),
|
|
.Dout(Dout));
|
|
|
|
initial begin
|
|
clk = 0;
|
|
reset = 0;
|
|
En = 2'b00;
|
|
Din = 9'b000000000;
|
|
#5
|
|
clk = 1;
|
|
#5
|
|
clk = 0;
|
|
reset = 0;
|
|
En = 2'b00;
|
|
Din = 9'b010101010;
|
|
#5
|
|
clk = 1;
|
|
#5
|
|
clk = 0;
|
|
reset = 1;
|
|
En = 2'b00;
|
|
Din = 9'b010101010;
|
|
#5
|
|
clk = 1;
|
|
#5
|
|
clk = 0;
|
|
reset = 0;
|
|
En = 2'b01;
|
|
Din = 9'b101010101;
|
|
#5
|
|
clk = 1;
|
|
#5
|
|
clk = 0;
|
|
reset = 0;
|
|
En = 2'b00;
|
|
Din = 9'b000011111;
|
|
#5
|
|
clk = 1;
|
|
#5
|
|
clk = 0;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module shift_left(
|
|
input wire [8:0] A,
|
|
output wire [8:0] B);
|
|
|
|
assign B = {A[7:0],1'b0};
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module shift_left_tb();
|
|
reg [8:0] a;
|
|
wire [8:0] b;
|
|
|
|
shift_left tb0(
|
|
.A(a),
|
|
.B(b));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
#5
|
|
a = 9'b000000001;
|
|
#5
|
|
a = 9'b000111000;
|
|
#5
|
|
a = 9'b010101010;
|
|
#5
|
|
a = 9'b101010101;
|
|
#5
|
|
a = 9'b111111111;
|
|
#5
|
|
a = 9'b100000001;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module shift_right_logical(
|
|
input wire [8:0] A,
|
|
output wire [8:0] B);
|
|
|
|
assign B = {1'b0,A[8:1]};
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module shift_right_logical_tb();
|
|
reg [8:0] a;
|
|
wire [8:0] b;
|
|
|
|
shift_right_logical tb0(
|
|
.A(a),
|
|
.B(b));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
#5
|
|
a = 9'b000000001;
|
|
#5
|
|
a = 9'b000111000;
|
|
#5
|
|
a = 9'b010101010;
|
|
#5
|
|
a = 9'b101010101;
|
|
#5
|
|
a = 9'b111111111;
|
|
#5
|
|
a = 9'b100000001;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module shift_right_arithmetic(
|
|
input wire [8:0] A,
|
|
output wire [8:0] B);
|
|
|
|
assign B = {A[8],A[8:1]};
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module shift_right_arithmetic_tb();
|
|
reg [8:0] a;
|
|
wire [8:0] b;
|
|
|
|
shift_right_arithmetic tb0(
|
|
.A(a),
|
|
.B(b));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
#5
|
|
a = 9'b000000001;
|
|
#5
|
|
a = 9'b000111000;
|
|
#5
|
|
a = 9'b010101010;
|
|
#5
|
|
a = 9'b101010101;
|
|
#5
|
|
a = 9'b111111111;
|
|
#5
|
|
a = 9'b100000001;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module slt (
|
|
input wire en,
|
|
input wire [8:0] inA, inB,
|
|
output reg outA);
|
|
|
|
always @(inA, inB)begin
|
|
if (inA < inB) begin
|
|
outA = 1;
|
|
end
|
|
else begin
|
|
outA = 0;
|
|
end
|
|
end
|
|
endmodule
|
|
|
|
//testbench
|
|
module slt_tb();
|
|
reg enable;
|
|
reg [8:0] indexA;
|
|
reg [8:0] indexB;
|
|
wire outputA;
|
|
|
|
slt slt0(
|
|
.en(enable),
|
|
.inA(indexA),
|
|
.inB(indexB),
|
|
.outA(outputA));
|
|
|
|
initial begin
|
|
enable = 0;
|
|
#5
|
|
enable = 1;
|
|
#5
|
|
indexA = 9'b000000000;
|
|
indexB = 9'b000000000;
|
|
#10
|
|
indexA = 9'b000000000;
|
|
indexB = 9'b111100000;
|
|
#10
|
|
indexA = 9'b000001111;
|
|
indexB = 9'b000000000;
|
|
#10
|
|
$finish;
|
|
end
|
|
endmodule
|
|
|
|
module sub_9bit(
|
|
input wire [8:0] A,
|
|
input wire [8:0] B,
|
|
output wire [8:0] C);
|
|
|
|
wire [8:0] D;
|
|
|
|
twos_compliment_9bit two_comp0(
|
|
.A(B),
|
|
.B(D));
|
|
|
|
add_9bit add0(
|
|
.A(A),
|
|
.B(D),
|
|
.Cin(1'b0),
|
|
.Sum(C));
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module sub_9bit_tb();
|
|
reg [8:0] a;
|
|
reg [8:0] b;
|
|
wire [8:0] c;
|
|
|
|
sub_9bit tb0(
|
|
.A(a),
|
|
.B(b),
|
|
.C(c));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
b = 9'b000000000;
|
|
#5
|
|
a = 9'b111111111;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b111111111;
|
|
b = 9'b000000000;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b010101010;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b010101010;
|
|
b = 9'b101010101;
|
|
#5
|
|
a = 9'b000011111;
|
|
b = 9'b111111111;
|
|
#5
|
|
a = 9'b000000000;
|
|
b = 9'b000010000;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule
|
|
|
|
module twos_compliment_9bit(
|
|
input wire [8:0] A,
|
|
output wire [8:0] B);
|
|
|
|
wire [8:0] C;
|
|
|
|
not_9bit not0(
|
|
.A(A),
|
|
.B(C));
|
|
|
|
add_9bit add0(
|
|
.A(C),
|
|
.B(9'b000000000),
|
|
.Cin(1'b1),
|
|
.Sum(B));
|
|
|
|
endmodule
|
|
|
|
//testbench
|
|
module twos_compliment_tb();
|
|
reg [8:0] a;
|
|
wire [8:0] b;
|
|
|
|
twos_compliment_9bit tb0(
|
|
.A(a),
|
|
.B(b));
|
|
|
|
initial begin
|
|
a = 9'b000000000;
|
|
#5
|
|
a = 9'b000000001;
|
|
#5
|
|
a = 9'b000111000;
|
|
#5
|
|
a = 9'b010101010;
|
|
#5
|
|
a = 9'b101010101;
|
|
#5
|
|
a = 9'b111111111;
|
|
#5
|
|
a = 9'b100000001;
|
|
#5
|
|
$finish;
|
|
|
|
end
|
|
endmodule |