2019-03-12 11:23:48 -04:00
CPU
2019-03-10 16:32:25 -04:00
2019-02-15 11:20:14 -05:00
2019-02-21 15:11:10 -05:00
CPU
2019-03-10 16:32:25 -04:00
2019-03-10 12:59:09 -04:00
2019-02-16 12:37:12 -05:00
2019-02-16 13:04:06 -05:00
2019-02-16 12:42:09 -05:00
2019-02-16 13:04:06 -05:00

ECE 3570 Lab

Fixes To Be Implemented

  • Get rid of the double zero for the enable on the registers
    • Make decoder for it
  • Redo simulations with other registers using internal signals
  • Fix simulation waveforms for Registers, as we are currently changing inputs too quickly (multiple times within a clock cycle)
  • Only two registers are being written to, first two within simulation is not being written to
  • Need to allow for signed numbers
  • Remove subtraction from ALU
  • Have arithmetic shift left and right
  • Uncomment all testbenches (We can have multiple testbenches active at once)
  • Bitwise operations do not need a 1-bit implementation, modify 9-bit and keep it only
  • Comparator needed
  • Make subtraction more efficient
  • Need to verify that FetchUnit is working properly as Martin had some concerns that it probably wasn't functioning properly
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