317 lines
8.9 KiB
Verilog
317 lines
8.9 KiB
Verilog
`timescale 1ns / 1ps
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module dataMemory(
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input wire clk, writeEnable,
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input wire [8:0] address, writeData,
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output reg [8:0] readData
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);
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reg [8:0] memory [1:0]; // Maximum of 512 memory locations
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// Vivado will give warnings of unconnected ports on the "address" bus if they are unused
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initial begin
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//Equation Solver Memory
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memory[0] <= 9'b000000001;
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memory[1] <= 9'b000000010;
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// String Compare Memory
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// memory[0] <= 9'b000000100;
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// memory[1] <= 9'b000001000;
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// memory[2] <= 9'b000001100;
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// memory[3] <= 9'b010101010;
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// memory[4] <= 9'b000001111;
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// memory[5] <= 9'b000000100;
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// memory[6] <= 9'b000000000;
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// memory[7] <= 9'b000000111;
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// memory[8] <= 9'b000001111;
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// memory[9] <= 9'b000000110;
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// memory[10] <= 9'b000000010;
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// memory[11] <= 9'b000000000;
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// memory[12] <= 9'b000000000;
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// memory[13] <= 9'b000000000;
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// memory[14] <= 9'b000000000;
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// memory[15] <= 9'b000000000;
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// Bubble Sort Initial Memory
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// memory[0] <= 9'b000010110;
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// memory[1] <= 9'b000100010;
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// memory[2] <= 9'b000100000;
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// memory[3] <= 9'b010001000;
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// memory[4] <= 9'b010010000;
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// memory[5] <= 9'b010011000;
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// memory[6] <= 9'b101001000;
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// memory[7] <= 9'b101001010;
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// memory[8] <= 9'b000100011;
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// memory[9] <= 9'b101001001;
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// memory[10] <= 9'b011001001;
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// memory[11] <= 9'b001001000;
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// memory[12] <= 9'b101001001;
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// memory[13] <= 9'b011101000;
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// memory[14] <= 9'b110001010;
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// memory[15] <= 9'b000100001;
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// memory[16] <= 9'b100110100;
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// memory[17] <= 9'b000001001;
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// memory[18] <= 9'b011001001;
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// memory[19] <= 9'b000110010;
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// memory[20] <= 9'b000000001;
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// memory[21] <= 9'b000111010;
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// memory[22] <= 9'b101011110;
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// memory[23] <= 9'b011111100;
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// Binary Search Memory
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// memory[0] <= 9'b000000000;
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// memory[1] <= 9'b000000111;
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// memory[2] <= 9'b000000001;
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// memory[3] <= 9'b000000010;
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// memory[4] <= 9'b000000011;
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// memory[5] <= 9'b000000100;
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// memory[6] <= 9'b000000101;
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// memory[7] <= 9'b000000110;
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// memory[8] <= 9'b000000111;
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// memory[9] <= 9'b000001000;
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// memory[10] <= 9'b000001001;
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// memory[11] <= 9'b000001010;
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// memory[12] <= 9'b000001011;
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// memory[13] <= 9'b000001100;
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// memory[14] <= 9'b000001101;
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// memory[15] <= 9'b000001110;
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// memory[16] <= 9'b000001111;
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// memory[17] <= 9'b000010000;
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// memory[18] <= 9'b000010001;
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// memory[19] <= 9'b000010010;
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// Program 1 Test Data
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memory[0] <= 9'd100;
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memory[1] <= 9'd58;
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memory[2] <= 9'd6;
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memory[3] <= 9'd12;
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memory[4] <= 9'b110110000; // -80
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memory[5] <= 9'd17;
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memory[6] <= 9'b111011011; // -37
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memory[7] <= 9'd25;
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memory[8] <= -9'd83; // -83
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memory[9] <= -9'd98; // -98
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memory[10] <= -9'd98; // -98
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memory[11] <= -9'd74; // -74
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memory[12] <= 9'd70;
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memory[13] <= -9'd38; // -38
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memory[14] <= 9'd52;
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memory[15] <= -9'd96; // -96
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memory[16] <= -9'd32; // -32
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memory[17] <= -9'd93; // -93
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memory[18] <= -9'd40; // -40
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memory[19] <= 9'd59;
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memory[20] <= 9'd10;
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memory[21] <= 9'd81;
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memory[22] <= -9'd23; // -28
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memory[23] <=- 9'd99; // -99
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memory[24] <= -9'd41; // -41
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memory[25] <= 9'd33;
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memory[26] <= 9'd98;
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memory[27] <= 9'd73;
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memory[28] <= -9'd1; // -1
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memory[29] <= 9'd28;
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memory[30] <= 9'd5;
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memory[31] <= -9'd74; // -74
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memory[32] <= -9'd41; // -41
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memory[33] <= 9'd41;
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memory[34] <= 9'd39;
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memory[35] <= 9'd62;
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memory[36] <= 9'd19;
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memory[37] <= -9'd40; // -40
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memory[38] <= -9'd8; // -8
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memory[39] <= 9'd92;
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memory[40] <= 9'd37;
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memory[41] <= 9'd50;
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memory[42] <= -9'd72; // -72
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memory[43] <= -9'd5; // -5
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memory[44] <= 9'd19;
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memory[45] <= 9'd58;
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memory[46] <= -9'd13; // -13
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memory[47] <= 9'd0;
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memory[48] <= -9'd97; // -97
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memory[49] <= 9'd54;
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memory[50] <= -9'd17; // -17
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memory[51] <= -9'd83; // -83
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memory[52] <= 9'd53;
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memory[53] <= 9'd82;
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memory[54] <= -9'd94; // -94
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memory[55] <= -9'd77; // -77
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memory[56] <= -9'd74; // -74
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memory[57] <= -9'd52; // -52
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memory[58] <= 9'd85;
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memory[59] <= -9'd65; // -65
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memory[60] <= -9'd10; // -10
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memory[61] <= -9'd45; // -45
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memory[62] <= -9'd92; // -92
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memory[63] <= -9'd30; // -30
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memory[64] <= 9'd18;
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memory[65] <= -9'd95; // -95
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memory[66] <= -9'd27; // -27
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memory[67] <= -9'd74; // -74
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memory[68] <= 9'd62;
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memory[69] <= 9'd64;
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memory[70] <= -9'd9; // -9
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memory[71] <= 9'd66;
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memory[72] <= -9'd71; // -71
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memory[73] <= -9'd31; // -31
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memory[74] <= 9'd34;
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memory[75] <= 9'd12;
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memory[76] <= 9'd3;
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memory[77] <= 9'd82;
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memory[78] <= 9'd13;
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memory[79] <= -9'd78; // -78
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memory[80] <= -9'd8; // -8
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memory[81] <= 9'd88;
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memory[82] <= 9'd42;
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memory[83] <= 9'd42;
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memory[84] <= 9'd21;
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memory[85] <= -9'd44; // -44
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memory[86] <= 9'd30;
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memory[87] <= -9'd93; // -93
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memory[88] <= 9'd2;
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memory[89] <= -9'd34; // -34
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memory[90] <= 9'd92;
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memory[91] <= -9'd45; // -45
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memory[92] <= 9'd26;
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memory[93] <= -9'd79; // -79
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memory[94] <= 9'd43;
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memory[95] <= -9'd25; // -25
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memory[96] <= -9'd24; // -24
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memory[97] <= -9'd25; // -25
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memory[98] <= -9'd19; // -19
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memory[99] <= -9'd49; // -49
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memory[100] <= -9'd8; // -8
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// Program 2 Test Data
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// memory[0] <= 9'd4;
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// memory[1] <= 9'd15;
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// memory[2] <= 9'b000001100;
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// memory[3] <= 9'b010101010;
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// memory[4] <= 9'h68; // h
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// memory[5] <= 9'h65; // e
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// memory[6] <= 9'h6C; // l
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// memory[7] <= 9'h6C; // l
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// memory[8] <= 9'h6F; // o
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// memory[9] <= 9'h20; // <space>
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// memory[10] <= 9'h77; // w
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// memory[11] <= 9'h6F; // o
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// memory[12] <= 9'h72; // r
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// memory[13] <= 9'h6C; // l
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// memory[14] <= 9'h64; // d
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// memory[15] <= 9'h68; // h
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// memory[16] <= 9'h65; // e
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// memory[17] <= 9'h6C; // l
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// memory[18] <= 9'h6C; // l
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// memory[19] <= 9'h6F; // o
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// memory[20] <= 9'h20; // <space>
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// memory[21] <= 9'h77; // w
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// memory[22] <= 9'h6F; // o
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// memory[23] <= 9'h72; // r
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// memory[24] <= 9'h6C; // l
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// memory[25] <= 9'h64; // d
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// Program 3 Test Data
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// memory[0] <= 9'd25; // 25
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// memory[1] <= -9'd3; // -3
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end
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always @ (posedge clk)
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begin
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if(writeEnable == 1'b1)
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memory[address] <= writeData;
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else
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readData <= memory[address];
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end
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endmodule
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module dataMemory_tb();
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reg clk, writeEnable;
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reg [8:0] address, writeData;
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wire [8:0] readData;
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always
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#5 clk = ~clk; // Period to be determined
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dataMemory dM0(
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.clk(clk),
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.writeEnable(writeEnable),
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.writeData(writeData),
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.address(address),
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.readData(readData)
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);
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initial
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begin
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clk = 1'b0;
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writeEnable = 1'b0;
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address = 9'b000000000;
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writeData = 9'b010101010;
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#5
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address = 9'b000000100;
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writeData = 9'b010101010;
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#10
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writeEnable = 1'b1;
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address = 9'b000000000;
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writeData = 9'b010101010;
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#10
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address = 9'b000000001;
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writeData = 9'b000001111;
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#10
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address = 9'b000000010;
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writeData = 9'b000000101;
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#10
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writeEnable = 1'b0;
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address = 9'b001000000;
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writeData = 9'b010101010;
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#10
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address = 9'b001000001;
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writeData = 9'b000001111;
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#10
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address = 9'b000011010;
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writeData = 9'b000000101;
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#10
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writeEnable = 1'b1;
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address = 9'b100111000;
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writeData = 9'b010101010;
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#10
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address = 9'b100100001;
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writeData = 9'b000001111;
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#10
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address = 9'b110000010;
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writeData = 9'b000000101;
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#10
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address = 9'b111110011;
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writeData = 9'b000000011;
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#10
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address = 9'b00000010;
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writeData = 9'b000001101;
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#5
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$finish;
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end
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endmodule
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