Made to write only once on positive edge of clock, Vivado now recognizes it as RTL_RAM

2019-03-29 16:13:50 -04:00
parent 5bd244f9ba
commit 352aeefd1b
1 changed files with 5 additions and 7 deletions
--- a/lab2CA.srcs/sources_1/new/dataMemory.v
+++ b/lab2CA.srcs/sources_1/new/dataMemory.v
@@ -239,14 +239,12 @@ module dataMemory(

    end

-    always @ (address, clk, memory) begin
-        if(clk == 1'b1)begin
+    always @ (posedge clk)
+    begin
+        if(writeEnable == 1'b1)
+            memory[address] <= writeData;
+        else
            readData <= memory[address];
-            if(writeEnable == 1'b1)
-                memory[address] <= writeData;
-            else
-                memory[address] <= memory[address];
-        end
    end      
 endmodule