Made to write only once on positive edge of clock, Vivado now recognizes it as RTL_RAM

lab2CA.srcs/sources_1/new/dataMemory.v

@@ -239,14 +239,12 @@ module dataMemory(
 
     end
 
-    always @ (address, clk, memory) begin
+    always @ (posedge clk)
-        if(clk == 1'b1)begin
+    begin
-            readData <= memory[address];
         if(writeEnable == 1'b1)
             memory[address] <= writeData;
         else
-                memory[address] <= memory[address];
+            readData <= memory[address];
-        end
     end      
 endmodule