William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Added SLT

Browse Source 
There is a testbench but when I try to run it on my computer it brings up some regFile simulation even though SLT is set to top. Not sure if its my pc or the code
This commit is contained in:
Johannes
2019-03-12 19:49:46 -04:00
parent 4a462752e9
commit 3f01492398
19 changed files with 306 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
lab2CA.runs/synth_1/gen_run.xml
View File

@@ -4,8 +4,6 @@
<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
<File Type="RDS-RDS" Name="FetchUnit.vds"/>
<File Type="RDS-DCP" Name="FetchUnit.dcp"/>
<File Type="RDS-UTIL" Name="FetchUnit_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="FetchUnit_utilization_synth.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">