Added SLT

There is a testbench but when I try to run it on my computer it brings up some regFile simulation even though SLT is set to top. Not sure if its my pc or the code

lab2CA.sim/sim_1/behav/xsim/slt_tb_vlog.prj

@@ -0,0 +1,9 @@
+# compile verilog/system verilog design source files
+verilog xil_defaultlib  \
+"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
+
+# compile glbl module
+verilog xil_defaultlib "glbl.v"
+
+# Do not sort compile order
+nosort