Added SLT

There is a testbench but when I try to run it on my computer it brings up some regFile simulation even though SLT is set to top. Not sure if its my pc or the code

lab2CA.srcs/sources_1/bd/design_1/design_1.bd

@@ -0,0 +1,11 @@
+{
+  "design": {
+    "design_info": {
+      "boundary_crc": "0x0",
+      "name": "design_1",
+      "synth_flow_mode": "Hierarchical",
+      "tool_version": "2018.3"
+    },
+    "design_tree": {}
+  }
+}

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -884,6 +884,52 @@ module shift_right_arithmetic_tb();
     end
 endmodule
 
+module slt (
+    input wire en,
+    input wire [8:0] inA, inB,
+    output reg outA);
+    
+    always @(inA, inB)begin
+        if (inA < inB) begin
+            outA = 1;
+        end
+        else begin
+            outA = 0;
+        end
+    end
+endmodule
+
+//testbench
+module slt_tb();
+    reg enable;
+    reg [8:0] indexA;
+    reg [8:0] indexB;
+    wire outputA;
+
+    slt slt0(
+        .en(enable),
+        .inA(indexA),
+        .inB(indexB),
+        .outA(outputA));
+    
+    initial begin
+        enable = 0;
+        #5
+        enable = 1;
+        #5
+        indexA = 9'b000000000;
+        indexB = 9'b000000000;
+        #10
+        indexA = 9'b000000000;
+        indexB = 9'b111100000;
+        #10
+        indexA = 9'b000001111;
+        indexB = 9'b000000000;
+        #10
+        $finish;
+    end
+endmodule
+
 module sub_9bit(
     input wire [8:0] A,
     input wire [8:0] B,