William/WMU-ECE-3570-Lab
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Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.
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goochey
2019-02-27 12:06:17 -05:00
parent 0104b0e689
commit c047c801aa
25 changed files with 428 additions and 69 deletions
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lab2CA.runs/synth_1/gen_run.xml
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@@ -4,6 +4,8 @@
<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
<File Type="RDS-RDS" Name="FetchUnit.vds"/>
<File Type="RDS-DCP" Name="FetchUnit.dcp"/>
<File Type="RDS-UTIL" Name="FetchUnit_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="FetchUnit_utilization_synth.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">