Lots of changes

Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -295,6 +295,52 @@ module and9bit_tb();
     end
 endmodule
 
+module decoder (
+    input wire en,
+    input wire [1:0] index,
+    output reg [3:0] regOut);
+    
+    always @(en, index)begin
+        if(en == 1)begin
+            case(index) 
+            2'b00: regOut <= 4'b0001; 
+            2'b01: regOut <= 4'b0010;
+            2'b10: regOut <= 4'b0100;
+            2'b11: regOut <= 4'b1000;
+            default: regOut <= 4'bxxxx; 
+        endcase 
+        end
+    end
+endmodule
+
+//testbench
+module decoder_tb();
+    reg enable;
+    reg [1:0] indexIn;
+    wire [3:0] regOut;
+
+    decoder dec0(
+        .en(enable),
+        .index(indexIn),
+        .regOut(regOut));
+    
+    initial begin
+        enable = 0;
+        indexIn = 2'b00;
+        #5
+        enable = 1;
+        #5
+        indexIn = 2'b01;
+        #5
+        indexIn = 2'b10;
+        #5
+        indexIn = 2'b11;
+        #5
+        $finish;
+
+    end
+endmodule
+
 module gen_clock();
     reg clk;
     initial begin
@@ -305,7 +351,7 @@ module gen_clock();
     end
 endmodule
 
-module mux_2_1 tb0(
+module mux_2_1(
     input wire switch,
     input wire [8:0] A,B,
     output reg [8:0] out);
@@ -850,7 +896,7 @@ endmodule
 
 module register(
     input wire clk, reset,
-    input wire [1:0] En,
+    input wire En,
     input wire [8:0] Din,
     output reg [8:0] Dout);
                 
@@ -858,7 +904,7 @@ module register(
         if (reset == 1'b1) begin
             Dout = 9'b000000000;
         end
-        else if (En == 2'b00) begin
+        else if (En == 1'b0) begin
             Dout = Din;
         end
         else begin

lab2CA.srcs/sources_1/new/FetchUnit.v

@@ -11,7 +11,7 @@ module FetchUnit(input wire clk, reset,
     register PC(
         .clk(clk),
         .reset(reset),
-        .En(2'b00),
+        .En(1'b0),
         .Din(result_m),
         .Dout(progC_out));
     //Adds 1 to the program counter
@@ -55,7 +55,7 @@ module fetchUnit_tb();
     initial begin
         reset = 0;
         opidx = 1'b1;
-        addr_in = 0'b000000000;
+        addr_in = 9'b000000000;
         #5
         reset = 1;
         #5

lab2CA.srcs/sources_1/new/RegFile.v

@@ -1,39 +1,46 @@
 `timescale 1ns / 1ps
 
-module RegFile(input wire clk, reset,
+module RegFile(input wire clk, reset, enable,
                 input wire [1:0] write_index, op0_idx, op1_idx,
                 input wire [8:0] write_data,
                 output wire [8:0] op0, op1);
     
+    wire [3:0] decOut;
     wire [8:0] r0_out, r1_out, r2_out, r3_out;
     
     // To select a register En input must be 2'b00
     
+    decoder d0(
+        .en(enable),
+        .index(write_index),
+        .regOut(decOut)
+    );
+    
     register r0(
         .clk(clk),
         .reset(reset),
-        .En({write_index[0], write_index[1]}),
+        .En(decOut[0]),
         .Din(write_data),
         .Dout(r0_out));
         
     register r1(
         .clk(clk),
         .reset(reset),
-        .En({write_index[0], ~write_index[1]}),
+        .En(decOut[1]),
         .Din(write_data),
         .Dout(r1_out));
         
     register r2(
         .clk(clk),
         .reset(reset),
-        .En({~write_index[0], write_index[1]}),
+        .En(decOut[2]),
         .Din(write_data),
         .Dout(r2_out));
         
     register r3(
         .clk(clk),
         .reset(reset),
-        .En({~write_index[0], ~write_index[1]}),
+        .En(decOut[4]),
         .Din(write_data),
         .Dout(r3_out));    
         
@@ -59,7 +66,7 @@ endmodule
 module regFile_tb();
     reg [8:0] write_d;
     reg [1:0] w_idx, op0_idx, op1_idx;
-    reg reset,clk;
+    reg reset,clk, enable;
     wire [8:0] op0,op1;
 
     initial begin
@@ -71,6 +78,7 @@ module regFile_tb();
 
     RegFile regFile0(
         .clk(clk),
+        .enable(enable),
         .reset(reset),
         .write_index(w_idx),
         .op0_idx(op0_idx),
@@ -85,6 +93,7 @@ module regFile_tb();
         reset = 1;
         #5
         reset = 0;
+        enable = 1;
         w_idx = 2'b00;
         op0_idx = 2'b00;
         op1_idx = 2'b00;