Lots of changes

Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.

lab2CA.srcs/sources_1/new/FetchUnit.v

@@ -11,7 +11,7 @@ module FetchUnit(input wire clk, reset,
     register PC(
         .clk(clk),
         .reset(reset),
-        .En(2'b00),
+        .En(1'b0),
         .Din(result_m),
         .Dout(progC_out));
     //Adds 1 to the program counter
@@ -55,7 +55,7 @@ module fetchUnit_tb();
     initial begin
         reset = 0;
         opidx = 1'b1;
-        addr_in = 0'b000000000;
+        addr_in = 9'b000000000;
         #5
         reset = 1;
         #5