Lots of changes

Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.

lab2CA.srcs/sources_1/new/RegFile.v

@@ -1,39 +1,46 @@
 `timescale 1ns / 1ps
 
-module RegFile(input wire clk, reset,
+module RegFile(input wire clk, reset, enable,
                 input wire [1:0] write_index, op0_idx, op1_idx,
                 input wire [8:0] write_data,
                 output wire [8:0] op0, op1);
     
+    wire [3:0] decOut;
     wire [8:0] r0_out, r1_out, r2_out, r3_out;
     
     // To select a register En input must be 2'b00
     
+    decoder d0(
+        .en(enable),
+        .index(write_index),
+        .regOut(decOut)
+    );
+    
     register r0(
         .clk(clk),
         .reset(reset),
-        .En({write_index[0], write_index[1]}),
+        .En(decOut[0]),
         .Din(write_data),
         .Dout(r0_out));
         
     register r1(
         .clk(clk),
         .reset(reset),
-        .En({write_index[0], ~write_index[1]}),
+        .En(decOut[1]),
         .Din(write_data),
         .Dout(r1_out));
         
     register r2(
         .clk(clk),
         .reset(reset),
-        .En({~write_index[0], write_index[1]}),
+        .En(decOut[2]),
         .Din(write_data),
         .Dout(r2_out));
         
     register r3(
         .clk(clk),
         .reset(reset),
-        .En({~write_index[0], ~write_index[1]}),
+        .En(decOut[4]),
         .Din(write_data),
         .Dout(r3_out));    
         
@@ -59,7 +66,7 @@ endmodule
 module regFile_tb();
     reg [8:0] write_d;
     reg [1:0] w_idx, op0_idx, op1_idx;
-    reg reset,clk;
+    reg reset,clk, enable;
     wire [8:0] op0,op1;
 
     initial begin
@@ -71,6 +78,7 @@ module regFile_tb();
 
     RegFile regFile0(
         .clk(clk),
+        .enable(enable),
         .reset(reset),
         .write_index(w_idx),
         .op0_idx(op0_idx),
@@ -85,6 +93,7 @@ module regFile_tb();
         reset = 1;
         #5
         reset = 0;
+        enable = 1;
         w_idx = 2'b00;
         op0_idx = 2'b00;
         op1_idx = 2'b00;