WilliamMiceli
b1f1a7339b
Minor adjustments
2019-04-10 12:52:42 -04:00
WilliamMiceli
dd7a319e92
Better indentation
2019-04-06 16:08:02 -04:00
jose.rodriguezlabra
08e3659ba3
Better Sim
2019-03-14 14:37:58 -04:00
jose.rodriguezlabra
11a1d99e92
Computer works (kinda)
2019-03-13 12:51:44 -04:00
jose.rodriguezlabra
026eb65861
Fixed bugs, finished BEQ, Added Halt
2019-03-13 11:14:52 -04:00
Johannes
460fc3e4ed
CPU
...
LOTS
2019-03-10 16:32:25 -04:00
goochey
c047c801aa
Lots of changes
...
Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.
2019-02-27 12:06:17 -05:00
WilliamMiceli
1734d58b47
Adjusted indentation of testbench code
2019-02-25 13:27:22 -05:00
WilliamMiceli
7c83a77713
Activated all testbenches
2019-02-25 12:51:34 -05:00
WilliamMiceli
6900e74405
Miscellaneous
2019-02-21 15:09:00 -05:00
goochey
6550b48599
fetch unit test
2019-02-20 11:31:25 -05:00
goochey
faf9f883dd
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
jose.rodriguezlabra
0d9cc2b890
Erased weird numbers
2019-02-16 12:50:02 -05:00
goochey
b2eb0da26c
Fetch Unit Again
...
I think I did it wrong
2019-02-16 12:36:26 -05:00
jose.rodriguezlabra
7aa2cfff2a
Modularized project; mux, clock, and reg done; Progress on RegFile
2019-02-15 12:24:26 -05:00
