WilliamMiceli
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9e9ff7935b
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Renamed shifting for incoming shift_right_arithmetic
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2019-03-12 10:54:45 -04:00 |
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Johannes
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460fc3e4ed
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CPU
LOTS
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2019-03-10 16:32:25 -04:00 |
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WilliamMiceli
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1734d58b47
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Adjusted indentation of testbench code
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2019-02-25 13:27:22 -05:00 |
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WilliamMiceli
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7c83a77713
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Activated all testbenches
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2019-02-25 12:51:34 -05:00 |
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goochey
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54cccd419f
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Lots
Lots
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2019-02-16 17:40:18 -05:00 |
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goochey
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faf9f883dd
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Collaborative - Fixes and Testbenches for Basic Modules so far
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2019-02-16 16:29:12 -05:00 |
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WilliamMiceli
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0b71b05c02
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All current arithmetic and logical operations are now implemented
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2019-02-15 17:51:05 -05:00 |
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WilliamMiceli
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6369170e41
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Comments and slight renames
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2019-02-15 17:49:12 -05:00 |
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WilliamMiceli
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b2dfc05db8
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Renamed some things; adder is now implemented in ALU
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2019-02-15 17:09:44 -05:00 |
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WilliamMiceli
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d6cee0483c
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ALU opcode is different from instruction opcode, so reducing to needed operations only
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2019-02-15 17:02:54 -05:00 |
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WilliamMiceli
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f4c923f60c
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Fixed ALU to use the inputs we're actually going to be giving it
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2019-02-15 16:19:42 -05:00 |
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WilliamMiceli
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365fb5f648
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Moved ALU from simulation sources to design sources
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2019-02-15 16:15:41 -05:00 |
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