c047c801aa
Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.
80 lines
3.6 KiB
XML
80 lines
3.6 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<wave_config>
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<wave_state>
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</wave_state>
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<db_ref_list>
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<db_ref path="regFile_tb_behav.wdb" id="1">
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<top_modules>
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<top_module name="glbl" />
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<top_module name="regFile_tb" />
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</top_modules>
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</db_ref>
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</db_ref_list>
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<zoom_setting>
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<ZoomStartTime time="0fs"></ZoomStartTime>
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<ZoomEndTime time="70000001fs"></ZoomEndTime>
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<Cursor1Time time="70000000fs"></Cursor1Time>
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</zoom_setting>
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<column_width_setting>
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<NameColumnWidth column_width="116"></NameColumnWidth>
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<ValueColumnWidth column_width="116"></ValueColumnWidth>
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</column_width_setting>
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<WVObjectSize size="14" />
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<wvobject fp_name="/regFile_tb/write_d" type="array">
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<obj_property name="ElementShortName">write_d[8:0]</obj_property>
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<obj_property name="ObjectShortName">write_d[8:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/regFile_tb/w_idx" type="array">
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<obj_property name="ElementShortName">w_idx[1:0]</obj_property>
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<obj_property name="ObjectShortName">w_idx[1:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/regFile_tb/op0_idx" type="array">
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<obj_property name="ElementShortName">op0_idx[1:0]</obj_property>
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<obj_property name="ObjectShortName">op0_idx[1:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/regFile_tb/op1_idx" type="array">
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<obj_property name="ElementShortName">op1_idx[1:0]</obj_property>
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<obj_property name="ObjectShortName">op1_idx[1:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/regFile_tb/reset" type="logic">
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<obj_property name="ElementShortName">reset</obj_property>
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<obj_property name="ObjectShortName">reset</obj_property>
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</wvobject>
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<wvobject fp_name="/regFile_tb/clk" type="logic">
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<obj_property name="ElementShortName">clk</obj_property>
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<obj_property name="ObjectShortName">clk</obj_property>
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</wvobject>
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<wvobject fp_name="/regFile_tb/enable" type="logic">
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<obj_property name="ElementShortName">enable</obj_property>
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<obj_property name="ObjectShortName">enable</obj_property>
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</wvobject>
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<wvobject fp_name="/regFile_tb/op0" type="array">
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<obj_property name="ElementShortName">op0[8:0]</obj_property>
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<obj_property name="ObjectShortName">op0[8:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/regFile_tb/op1" type="array">
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<obj_property name="ElementShortName">op1[8:0]</obj_property>
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<obj_property name="ObjectShortName">op1[8:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/regFile_tb/regFile0/decOut" type="array">
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<obj_property name="ElementShortName">decOut[3:0]</obj_property>
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<obj_property name="ObjectShortName">decOut[3:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/regFile_tb/regFile0/r0_out" type="array">
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<obj_property name="ElementShortName">r0_out[8:0]</obj_property>
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<obj_property name="ObjectShortName">r0_out[8:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/regFile_tb/regFile0/r1_out" type="array">
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<obj_property name="ElementShortName">r1_out[8:0]</obj_property>
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<obj_property name="ObjectShortName">r1_out[8:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/regFile_tb/regFile0/r2_out" type="array">
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<obj_property name="ElementShortName">r2_out[8:0]</obj_property>
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<obj_property name="ObjectShortName">r2_out[8:0]</obj_property>
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</wvobject>
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<wvobject fp_name="/regFile_tb/regFile0/r3_out" type="array">
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<obj_property name="ElementShortName">r3_out[8:0]</obj_property>
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<obj_property name="ObjectShortName">r3_out[8:0]</obj_property>
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</wvobject>
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</wave_config>
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