Fixed bugs, finished BEQ, Added Halt
This commit is contained in:
jose.rodriguezlabra
@@ -3,10 +3,10 @@
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||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
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||||
The structure and the elements are likely to change over the next few releases.
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This means code written to parse this file will need to be revisited each subsequent release.-->
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<application name="pa" timeStamp="Tue Mar 12 23:04:24 2019">
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||||
<application name="pa" timeStamp="Wed Mar 13 11:12:12 2019">
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||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="88e779ed22f94d2db93b335d17c75f15" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="7" type="ProjectIteration"/>
|
||||
<property name="ProjectIteration" value="12" type="ProjectIteration"/>
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||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
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||||
@@ -21,53 +21,67 @@ This means code written to parse this file will need to be revisited each subseq
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<property name="OpenDesign" value="1" type="JavaHandler"/>
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||||
<property name="OpenProject" value="3" type="JavaHandler"/>
|
||||
<property name="ReloadDesign" value="1" type="JavaHandler"/>
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||||
<property name="RunImplementation" value="7" type="JavaHandler"/>
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||||
<property name="RunSchematic" value="9" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="16" type="JavaHandler"/>
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||||
<property name="ReportTimingSummary" value="3" type="JavaHandler"/>
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||||
<property name="RunImplementation" value="15" type="JavaHandler"/>
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||||
<property name="RunSchematic" value="13" type="JavaHandler"/>
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||||
<property name="RunSynthesis" value="18" type="JavaHandler"/>
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||||
<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
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||||
<property name="SetSourceEnabled" value="2" type="JavaHandler"/>
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||||
<property name="SetTopNode" value="26" type="JavaHandler"/>
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||||
<property name="ShowView" value="9" type="JavaHandler"/>
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||||
<property name="ShowView" value="11" type="JavaHandler"/>
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||||
<property name="SimulationClose" value="5" type="JavaHandler"/>
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||||
<property name="SimulationRun" value="74" type="JavaHandler"/>
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||||
<property name="TclFind" value="4" type="JavaHandler"/>
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||||
<property name="ToggleSelectAreaMode" value="2" type="JavaHandler"/>
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||||
<property name="ToolsSettings" value="1" type="JavaHandler"/>
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||||
<property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
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||||
<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
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||||
<property name="ViewTaskRTLAnalysis" value="2" type="JavaHandler"/>
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||||
<property name="ViewTaskRTLAnalysis" value="6" type="JavaHandler"/>
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||||
<property name="ZoomFit" value="6" type="JavaHandler"/>
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||||
<property name="ZoomOut" value="1" type="JavaHandler"/>
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</item>
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||||
<item name="Gui Handlers">
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||||
<property name="AbstractSearchablePanel_SHOW_SEARCH" value="1" type="GuiHandlerData"/>
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||||
<property name="BaseDialog_CANCEL" value="13" type="GuiHandlerData"/>
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<property name="BaseDialog_OK" value="67" type="GuiHandlerData"/>
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<property name="BaseDialog_YES" value="5" type="GuiHandlerData"/>
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<property name="CmdMsgDialog_OK" value="7" type="GuiHandlerData"/>
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<property name="BaseDialog_CANCEL" value="20" type="GuiHandlerData"/>
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<property name="BaseDialog_OK" value="88" type="GuiHandlerData"/>
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<property name="BaseDialog_YES" value="10" type="GuiHandlerData"/>
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<property name="ClosePlanner_YES" value="1" type="GuiHandlerData"/>
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<property name="CmdMsgDialog_MESSAGES" value="2" type="GuiHandlerData"/>
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<property name="CmdMsgDialog_OK" value="11" type="GuiHandlerData"/>
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<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/>
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||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="208" type="GuiHandlerData"/>
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||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="224" type="GuiHandlerData"/>
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||||
<property name="FloatingTopDialog_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="12" type="GuiHandlerData"/>
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<property name="FloatingTopDialog_SPECIFY_NEW_TOP_MODULE" value="10" type="GuiHandlerData"/>
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||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="133" type="GuiHandlerData"/>
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||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="160" type="GuiHandlerData"/>
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||||
<property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
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<property name="GraphicalView_ZOOM_FIT" value="27" type="GuiHandlerData"/>
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<property name="GraphicalView_ZOOM_IN" value="40" type="GuiHandlerData"/>
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<property name="GraphicalView_ZOOM_OUT" value="28" type="GuiHandlerData"/>
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||||
<property name="HCodeEditor_BLANK_OPERATIONS" value="5" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_CLOSE" value="4" type="GuiHandlerData"/>
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||||
<property name="HCodeEditor_BLANK_OPERATIONS" value="6" type="GuiHandlerData"/>
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||||
<property name="HCodeEditor_CLOSE" value="9" type="GuiHandlerData"/>
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<property name="HCodeEditor_COMMANDS_TO_FOLD_TEXT" value="3" type="GuiHandlerData"/>
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||||
<property name="HCodeEditor_DIFF_WITH" value="3" type="GuiHandlerData"/>
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||||
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="10" type="GuiHandlerData"/>
|
||||
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="31" type="GuiHandlerData"/>
|
||||
<property name="HInputHandler_INDENT_SELECTION" value="1" type="GuiHandlerData"/>
|
||||
<property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="13" type="GuiHandlerData"/>
|
||||
<property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="15" type="GuiHandlerData"/>
|
||||
<property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
|
||||
<property name="LaunchPanel_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
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||||
<property name="MainMenuMgr_EDIT" value="2" type="GuiHandlerData"/>
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||||
<property name="MainMenuMgr_FILE" value="12" type="GuiHandlerData"/>
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||||
<property name="MainMenuMgr_FLOW" value="2" type="GuiHandlerData"/>
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||||
<property name="MainMenuMgr_PROJECT" value="7" type="GuiHandlerData"/>
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||||
<property name="MainMenuMgr_WINDOW" value="2" type="GuiHandlerData"/>
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||||
<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="2" type="GuiHandlerData"/>
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||||
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="29" type="GuiHandlerData"/>
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||||
<property name="MsgTreePanel_MESSAGE_SEVERITY" value="2" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="96" type="GuiHandlerData"/>
|
||||
<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="5" type="GuiHandlerData"/>
|
||||
<property name="MsgView_WARNING_MESSAGES" value="3" type="GuiHandlerData"/>
|
||||
<property name="NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE" value="61" type="GuiHandlerData"/>
|
||||
<property name="NetlistTreeView_NETLIST_TREE" value="1" type="GuiHandlerData"/>
|
||||
<property name="OpenFileAction_OK" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_UPDATE_HIER" value="29" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_CLOSE_PROJECT" value="4" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_MESSAGE_WINDOW" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_RTL_DESIGN" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RELOAD_RTL_DESIGN" value="1" type="GuiHandlerData"/>
|
||||
@@ -79,35 +93,37 @@ This means code written to parse this file will need to be revisited each subseq
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<property name="PACommandNames_SIMULATION_SETTINGS" value="1" type="GuiHandlerData"/>
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||||
<property name="PACommandNames_SRC_ENABLE" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ZOOM_FIT" value="6" type="GuiHandlerData"/>
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||||
<property name="PACommandNames_ZOOM_OUT" value="1" type="GuiHandlerData"/>
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||||
<property name="PAViews_CODE" value="13" type="GuiHandlerData"/>
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||||
<property name="PAViews_PROJECT_SUMMARY" value="43" type="GuiHandlerData"/>
|
||||
<property name="PAViews_SCHEMATIC" value="9" type="GuiHandlerData"/>
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||||
<property name="PAViews_SCHEMATIC" value="10" type="GuiHandlerData"/>
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||||
<property name="ProgressDialog_BACKGROUND" value="3" type="GuiHandlerData"/>
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||||
<property name="ProgressDialog_CANCEL" value="4" type="GuiHandlerData"/>
|
||||
<property name="ProjectTab_RELOAD" value="8" type="GuiHandlerData"/>
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||||
<property name="ProjectTab_RELOAD" value="12" type="GuiHandlerData"/>
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||||
<property name="RDICommands_COPY" value="2" type="GuiHandlerData"/>
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||||
<property name="RDICommands_REDO" value="1" type="GuiHandlerData"/>
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||||
<property name="RDICommands_SAVE_FILE" value="70" type="GuiHandlerData"/>
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||||
<property name="RDICommands_SAVE_FILE" value="71" type="GuiHandlerData"/>
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||||
<property name="RDIViews_WAVEFORM_VIEWER" value="379" type="GuiHandlerData"/>
|
||||
<property name="ReportTimingSummaryDialog_REPORT_TIMING_SUMMARY_DIALOG_TABBED" value="12" type="GuiHandlerData"/>
|
||||
<property name="ReportTimingSummaryDialog_REPORT_UNCONSTRAINED_PATHS" value="2" type="GuiHandlerData"/>
|
||||
<property name="RunGadget_SHOW_ERROR" value="1" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="5" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="9" type="GuiHandlerData"/>
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||||
<property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="12" type="GuiHandlerData"/>
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||||
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="12" type="GuiHandlerData"/>
|
||||
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="10" type="GuiHandlerData"/>
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||||
<property name="SrcMenu_IP_HIERARCHY" value="30" type="GuiHandlerData"/>
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||||
<property name="StaleMoreAction_OUT_OF_DATE_DETAILS" value="1" type="GuiHandlerData"/>
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||||
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="9" type="GuiHandlerData"/>
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||||
<property name="StaleRunDialog_NO" value="1" type="GuiHandlerData"/>
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||||
<property name="StaleRunDialog_YES" value="1" type="GuiHandlerData"/>
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||||
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="10" type="GuiHandlerData"/>
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||||
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
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||||
<property name="TaskBanner_CLOSE" value="21" type="GuiHandlerData"/>
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||||
<property name="TaskBanner_CLOSE" value="25" type="GuiHandlerData"/>
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||||
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/>
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||||
<property name="TclFindDialog_RESULT_NAME" value="2" type="GuiHandlerData"/>
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||||
<property name="TimingDialogUtils_RESULTS_NAME" value="1" type="GuiHandlerData"/>
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||||
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="187" type="GuiHandlerData"/>
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||||
</item>
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||||
<item name="Other">
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||||
<property name="GuiMode" value="63" type="GuiMode"/>
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||||
<property name="BatchMode" value="0" type="BatchMode"/>
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||||
<property name="TclMode" value="62" type="TclMode"/>
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||||
</item>
|
||||
</section>
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||||
</application>
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||||
</document>
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8
lab2CA.runs/.jobs/vrs_config_24.xml
Normal file
8
lab2CA.runs/.jobs/vrs_config_24.xml
Normal file
@@ -0,0 +1,8 @@
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<?xml version="1.0"?>
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<Runs Version="1" Minor="0">
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<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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||||
<Parameters>
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||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
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||||
</Parameters>
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||||
</Runs>
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||||
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8
lab2CA.runs/.jobs/vrs_config_25.xml
Normal file
8
lab2CA.runs/.jobs/vrs_config_25.xml
Normal file
@@ -0,0 +1,8 @@
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<?xml version="1.0"?>
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||||
<Runs Version="1" Minor="0">
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||||
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
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||||
</Parameters>
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||||
</Runs>
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||||
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||||
11
lab2CA.runs/.jobs/vrs_config_26.xml
Normal file
11
lab2CA.runs/.jobs/vrs_config_26.xml
Normal file
@@ -0,0 +1,11 @@
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<?xml version="1.0"?>
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<Runs Version="1" Minor="0">
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||||
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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||||
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
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||||
<Parent Id="synth_1"/>
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||||
</Run>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
11
lab2CA.runs/.jobs/vrs_config_27.xml
Normal file
11
lab2CA.runs/.jobs/vrs_config_27.xml
Normal file
@@ -0,0 +1,11 @@
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||||
<?xml version="1.0"?>
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||||
<Runs Version="1" Minor="0">
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||||
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
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||||
<Parent Id="synth_1"/>
|
||||
</Run>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
11
lab2CA.runs/.jobs/vrs_config_28.xml
Normal file
11
lab2CA.runs/.jobs/vrs_config_28.xml
Normal file
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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||||
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
|
||||
<Parent Id="synth_1"/>
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||||
</Run>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
11
lab2CA.runs/.jobs/vrs_config_29.xml
Normal file
11
lab2CA.runs/.jobs/vrs_config_29.xml
Normal file
@@ -0,0 +1,11 @@
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||||
<?xml version="1.0"?>
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||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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||||
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
|
||||
<Parent Id="synth_1"/>
|
||||
</Run>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
11
lab2CA.runs/.jobs/vrs_config_30.xml
Normal file
11
lab2CA.runs/.jobs/vrs_config_30.xml
Normal file
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
|
||||
<Parent Id="synth_1"/>
|
||||
</Run>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
@@ -60,6 +60,8 @@ proc step_failed { step } {
|
||||
close $ch
|
||||
}
|
||||
|
||||
set_msg_config -id {Synth 8-256} -limit 10000
|
||||
set_msg_config -id {Synth 8-638} -limit 10000
|
||||
|
||||
start_step init_design
|
||||
set ACTIVE_STEP init_design
|
||||
@@ -68,12 +70,12 @@ set rc [catch {
|
||||
create_project -in_memory -part xc7k160tifbg484-2L
|
||||
set_property design_mode GateLvl [current_fileset]
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project]
|
||||
set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project]
|
||||
set_property ip_output_repo C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project]
|
||||
set_property webtalk.parent_dir {C:/Users/JoseIgnacio/CA Lab/lab2CA.cache/wt} [current_project]
|
||||
set_property parent.project_path {C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr} [current_project]
|
||||
set_property ip_output_repo {{C:/Users/JoseIgnacio/CA Lab/lab2CA.cache/ip}} [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
add_files -quiet C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.dcp
|
||||
link_design -top FetchUnit -part xc7k160tifbg484-2L
|
||||
add_files -quiet {{C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.dcp}}
|
||||
link_design -top CPU9bits -part xc7k160tifbg484-2L
|
||||
close_msg_db -file init_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
@@ -89,8 +91,8 @@ set ACTIVE_STEP opt_design
|
||||
set rc [catch {
|
||||
create_msg_db opt_design.pb
|
||||
opt_design
|
||||
write_checkpoint -force FetchUnit_opt.dcp
|
||||
create_report "impl_1_opt_report_drc_0" "report_drc -file FetchUnit_drc_opted.rpt -pb FetchUnit_drc_opted.pb -rpx FetchUnit_drc_opted.rpx"
|
||||
write_checkpoint -force CPU9bits_opt.dcp
|
||||
create_report "impl_1_opt_report_drc_0" "report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx"
|
||||
close_msg_db -file opt_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
@@ -109,10 +111,10 @@ set rc [catch {
|
||||
implement_debug_core
|
||||
}
|
||||
place_design
|
||||
write_checkpoint -force FetchUnit_placed.dcp
|
||||
create_report "impl_1_place_report_io_0" "report_io -file FetchUnit_io_placed.rpt"
|
||||
create_report "impl_1_place_report_utilization_0" "report_utilization -file FetchUnit_utilization_placed.rpt -pb FetchUnit_utilization_placed.pb"
|
||||
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file FetchUnit_control_sets_placed.rpt"
|
||||
write_checkpoint -force CPU9bits_placed.dcp
|
||||
create_report "impl_1_place_report_io_0" "report_io -file CPU9bits_io_placed.rpt"
|
||||
create_report "impl_1_place_report_utilization_0" "report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb"
|
||||
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt"
|
||||
close_msg_db -file place_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
@@ -128,19 +130,19 @@ set ACTIVE_STEP route_design
|
||||
set rc [catch {
|
||||
create_msg_db route_design.pb
|
||||
route_design
|
||||
write_checkpoint -force FetchUnit_routed.dcp
|
||||
create_report "impl_1_route_report_drc_0" "report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx"
|
||||
create_report "impl_1_route_report_methodology_0" "report_methodology -file FetchUnit_methodology_drc_routed.rpt -pb FetchUnit_methodology_drc_routed.pb -rpx FetchUnit_methodology_drc_routed.rpx"
|
||||
create_report "impl_1_route_report_power_0" "report_power -file FetchUnit_power_routed.rpt -pb FetchUnit_power_summary_routed.pb -rpx FetchUnit_power_routed.rpx"
|
||||
create_report "impl_1_route_report_route_status_0" "report_route_status -file FetchUnit_route_status.rpt -pb FetchUnit_route_status.pb"
|
||||
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file FetchUnit_timing_summary_routed.rpt -pb FetchUnit_timing_summary_routed.pb -rpx FetchUnit_timing_summary_routed.rpx -warn_on_violation "
|
||||
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file FetchUnit_incremental_reuse_routed.rpt"
|
||||
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file FetchUnit_clock_utilization_routed.rpt"
|
||||
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file FetchUnit_bus_skew_routed.rpt -pb FetchUnit_bus_skew_routed.pb -rpx FetchUnit_bus_skew_routed.rpx"
|
||||
write_checkpoint -force CPU9bits_routed.dcp
|
||||
create_report "impl_1_route_report_drc_0" "report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx"
|
||||
create_report "impl_1_route_report_methodology_0" "report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx"
|
||||
create_report "impl_1_route_report_power_0" "report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx"
|
||||
create_report "impl_1_route_report_route_status_0" "report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb"
|
||||
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation "
|
||||
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file CPU9bits_incremental_reuse_routed.rpt"
|
||||
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt"
|
||||
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx"
|
||||
close_msg_db -file route_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
write_checkpoint -force FetchUnit_routed_error.dcp
|
||||
write_checkpoint -force CPU9bits_routed_error.dcp
|
||||
step_failed route_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
@@ -2,27 +2,27 @@
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Wed Feb 20 11:36:21 2019
|
||||
# Process ID: 644
|
||||
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
|
||||
# Command line: vivado.exe -log FetchUnit.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source FetchUnit.tcl -notrace
|
||||
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit.vdi
|
||||
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
|
||||
# Start of session at: Wed Mar 13 11:12:42 2019
|
||||
# Process ID: 11884
|
||||
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1
|
||||
# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
|
||||
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits.vdi
|
||||
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source FetchUnit.tcl -notrace
|
||||
Command: link_design -top FetchUnit -part xc7k160tifbg484-2L
|
||||
source CPU9bits.tcl -notrace
|
||||
Command: link_design -top CPU9bits -part xc7k160tifbg484-2L
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2018.3
|
||||
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 577.652 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 583.273 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:16 . Memory (MB): peak = 583.164 ; gain = 318.402
|
||||
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 588.785 ; gain = 334.348
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
|
||||
@@ -33,53 +33,53 @@ INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.704 . Memory (MB): peak = 597.828 ; gain = 14.664
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.165 . Memory (MB): peak = 592.141 ; gain = 3.355
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Ending Cache Timing Information Task | Checksum: 6a15e7bd
|
||||
Ending Cache Timing Information Task | Checksum: 16212f689
|
||||
|
||||
Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1157.887 ; gain = 560.059
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1080.938 ; gain = 488.797
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: 6a15e7bd
|
||||
Phase 1 Retarget | Checksum: 16212f689
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1254.445 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1175.109 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: 6a15e7bd
|
||||
Phase 2 Constant propagation | Checksum: 16212f689
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1254.445 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1175.109 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 6a15e7bd
|
||||
Phase 3 Sweep | Checksum: 16212f689
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1254.445 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1175.109 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
Phase 4 BUFG optimization | Checksum: 6a15e7bd
|
||||
Phase 4 BUFG optimization | Checksum: 16212f689
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1254.445 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1175.109 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
Phase 5 Shift Register Optimization | Checksum: 6a15e7bd
|
||||
Phase 5 Shift Register Optimization | Checksum: 16212f689
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.072 . Memory (MB): peak = 1254.445 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.087 . Memory (MB): peak = 1175.109 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: 6a15e7bd
|
||||
Phase 6 Post Processing Netlist | Checksum: 16212f689
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.073 . Memory (MB): peak = 1254.445 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.087 . Memory (MB): peak = 1175.109 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
@@ -100,42 +100,42 @@ Opt_design Change Summary
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1254.445 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 6a15e7bd
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1175.109 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 16212f689
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1254.445 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 1175.109 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 6a15e7bd
|
||||
Ending Power Optimization Task | Checksum: 16212f689
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1254.445 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1175.109 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 6a15e7bd
|
||||
Ending Final Cleanup Task | Checksum: 16212f689
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1254.445 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1175.109 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1254.445 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 6a15e7bd
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1175.109 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 16212f689
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1254.445 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1175.109 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1254.445 ; gain = 671.281
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1254.445 ; gain = 0.000
|
||||
opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1175.109 ; gain = 586.324
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1175.109 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file FetchUnit_drc_opted.rpt -pb FetchUnit_drc_opted.pb -rpx FetchUnit_drc_opted.rpx
|
||||
Command: report_drc -file FetchUnit_drc_opted.rpt -pb FetchUnit_drc_opted.pb -rpx FetchUnit_drc_opted.rpx
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
|
||||
Command: report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_drc_opted.rpt.
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
|
||||
@@ -154,127 +154,57 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1254.445 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2dee624c
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1195.590 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 9761e0e0
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1254.445 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1254.445 ; gain = 0.000
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1195.590 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1195.590 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f86a639b
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 19236f07e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.988 ; gain = 6.543
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 1b3769117
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 1e494ed1a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.988 ; gain = 6.543
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 1b3769117
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 1e494ed1a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.988 ; gain = 6.543
|
||||
Phase 1 Placer Initialization | Checksum: 1b3769117
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
|
||||
Phase 1 Placer Initialization | Checksum: 1e494ed1a
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.988 ; gain = 6.543
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
|
||||
|
||||
Phase 2 Global Placement
|
||||
Phase 2 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.129 ; gain = 0.000
|
||||
Phase 2 Final Placement Cleanup | Checksum: 1e494ed1a
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 1b3769117
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
|
||||
INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed
|
||||
Ending Placer Task | Checksum: 19236f07e
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1262.563 ; gain = 8.117
|
||||
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
|
||||
Phase 2 Global Placement | Checksum: fdf1e15d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1271.574 ; gain = 17.129
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: fdf1e15d
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1271.574 ; gain = 17.129
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 172140857
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1271.574 ; gain = 17.129
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 18b28c28e
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1271.574 ; gain = 17.129
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 18b28c28e
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1271.574 ; gain = 17.129
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 1814d396b
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 1814d396b
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 1814d396b
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
|
||||
Phase 3 Detail Placement | Checksum: 1814d396b
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 1814d396b
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 1814d396b
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
Phase 4.3 Placer Reporting | Checksum: 1814d396b
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1281.449 ; gain = 0.000
|
||||
Phase 4.4 Final Placement Cleanup | Checksum: 20047366c
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 20047366c
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
|
||||
Ending Placer Task | Checksum: 127ea04eb
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
37 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
38 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1281.449 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1204.129 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 1281.449 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file FetchUnit_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.058 . Memory (MB): peak = 1281.449 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file FetchUnit_utilization_placed.rpt -pb FetchUnit_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file FetchUnit_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1281.449 ; gain = 0.000
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.122 . Memory (MB): peak = 1204.129 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file CPU9bits_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.086 . Memory (MB): peak = 1210.254 ; gain = 6.125
|
||||
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1210.254 ; gain = 0.000
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
|
||||
@@ -286,68 +216,67 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
Checksum: PlaceDB: 884dbbb5 ConstDB: 0 ShapeSum: 9f9c4936 RouteDB: 0
|
||||
Checksum: PlaceDB: fad50f9e ConstDB: 0 ShapeSum: 9761e0e0 RouteDB: 0
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Phase 1 Build RT Design | Checksum: c942aae2
|
||||
Phase 1 Build RT Design | Checksum: ae2d8a92
|
||||
|
||||
Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 1488.156 ; gain = 206.707
|
||||
Post Restoration Checksum: NetGraph: 96738515 NumContArr: 32cf25cd Constraints: 0 Timing: 0
|
||||
Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.336 ; gain = 223.395
|
||||
Post Restoration Checksum: NetGraph: 87f14705 NumContArr: 263c438d Constraints: 0 Timing: 0
|
||||
|
||||
Phase 2 Router Initialization
|
||||
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
|
||||
|
||||
Phase 2.1 Fix Topology Constraints
|
||||
Phase 2.1 Fix Topology Constraints | Checksum: c942aae2
|
||||
Phase 2.1 Fix Topology Constraints | Checksum: ae2d8a92
|
||||
|
||||
Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 1492.688 ; gain = 211.238
|
||||
Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 1440.074 ; gain = 227.133
|
||||
|
||||
Phase 2.2 Pre Route Cleanup
|
||||
Phase 2.2 Pre Route Cleanup | Checksum: c942aae2
|
||||
Phase 2.2 Pre Route Cleanup | Checksum: ae2d8a92
|
||||
|
||||
Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 1492.688 ; gain = 211.238
|
||||
Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 1440.074 ; gain = 227.133
|
||||
Number of Nodes with overlaps = 0
|
||||
Phase 2 Router Initialization | Checksum: a27c41a8
|
||||
Phase 2 Router Initialization | Checksum: 6e1873f8
|
||||
|
||||
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.094 ; gain = 234.645
|
||||
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1448.008 ; gain = 235.066
|
||||
|
||||
Phase 3 Initial Routing
|
||||
Phase 3 Initial Routing | Checksum: 15301da77
|
||||
Number of Nodes with overlaps = 0
|
||||
Phase 3 Initial Routing | Checksum: 6e1873f8
|
||||
|
||||
Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.094 ; gain = 234.645
|
||||
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 1
|
||||
Number of Nodes with overlaps = 0
|
||||
Phase 4.1 Global Iteration 0 | Checksum: af31d432
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 6e1873f8
|
||||
|
||||
Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
|
||||
Phase 4 Rip-up And Reroute | Checksum: af31d432
|
||||
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
|
||||
Phase 4 Rip-up And Reroute | Checksum: 6e1873f8
|
||||
|
||||
Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
|
||||
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
Phase 5 Delay and Skew Optimization | Checksum: af31d432
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 6e1873f8
|
||||
|
||||
Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
|
||||
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
Phase 6.1 Hold Fix Iter | Checksum: af31d432
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 6e1873f8
|
||||
|
||||
Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
|
||||
Phase 6 Post Hold Fix | Checksum: af31d432
|
||||
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
|
||||
Phase 6 Post Hold Fix | Checksum: 6e1873f8
|
||||
|
||||
Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
|
||||
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.00297689 %
|
||||
Global Horizontal Routing Utilization = 0.00221654 %
|
||||
Global Vertical Routing Utilization = 0 %
|
||||
Global Horizontal Routing Utilization = 0 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
@@ -357,10 +286,10 @@ Router Utilization Summary
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Congestion Report
|
||||
North Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions.
|
||||
South Dir 1x1 Area, Max Cong = 25.2252%, No Congested Regions.
|
||||
East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions.
|
||||
West Dir 1x1 Area, Max Cong = 16.1765%, No Congested Regions.
|
||||
North Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
|
||||
South Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
|
||||
East Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
|
||||
West Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
|
||||
|
||||
------------------------------
|
||||
Reporting congestion hotspots
|
||||
@@ -382,70 +311,70 @@ Direction: West
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: af31d432
|
||||
Phase 7 Route finalize | Checksum: 6e1873f8
|
||||
|
||||
Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
|
||||
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: af31d432
|
||||
Phase 8 Verifying routed nets | Checksum: 6e1873f8
|
||||
|
||||
Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
|
||||
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1454.441 ; gain = 241.500
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 4b1641fa
|
||||
Phase 9 Depositing Routes | Checksum: 6e1873f8
|
||||
|
||||
Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
|
||||
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1454.441 ; gain = 241.500
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
|
||||
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1454.441 ; gain = 241.500
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
49 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
50 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 1516.094 ; gain = 234.645
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1516.094 ; gain = 0.000
|
||||
route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:32 . Memory (MB): peak = 1454.441 ; gain = 244.188
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1454.441 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1516.094 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx
|
||||
Command: report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1454.441 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
|
||||
Command: report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_drc_routed.rpt.
|
||||
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file FetchUnit_methodology_drc_routed.rpt -pb FetchUnit_methodology_drc_routed.pb -rpx FetchUnit_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file FetchUnit_methodology_drc_routed.rpt -pb FetchUnit_methodology_drc_routed.pb -rpx FetchUnit_methodology_drc_routed.rpx
|
||||
INFO: [runtcl-4] Executing : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_methodology_drc_routed.rpt.
|
||||
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file FetchUnit_power_routed.rpt -pb FetchUnit_power_summary_routed.pb -rpx FetchUnit_power_routed.rpx
|
||||
Command: report_power -file FetchUnit_power_routed.rpt -pb FetchUnit_power_summary_routed.pb -rpx FetchUnit_power_routed.rpx
|
||||
INFO: [runtcl-4] Executing : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
|
||||
Command: report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
|
||||
WARNING: [Power 33-232] No user defined clocks were found in the design!
|
||||
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
60 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
61 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file FetchUnit_route_status.rpt -pb FetchUnit_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file FetchUnit_timing_summary_routed.rpt -pb FetchUnit_timing_summary_routed.pb -rpx FetchUnit_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [runtcl-4] Executing : report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file FetchUnit_incremental_reuse_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file CPU9bits_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file FetchUnit_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file FetchUnit_bus_skew_routed.rpt -pb FetchUnit_bus_skew_routed.pb -rpx FetchUnit_bus_skew_routed.rpx
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Feb 20 11:37:30 2019...
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Mar 13 11:13:49 2019...
|
||||
@@ -1,13 +1,13 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Wed Feb 20 11:37:30 2019
|
||||
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
| Command : report_bus_skew -warn_on_violation -file FetchUnit_bus_skew_routed.rpt -pb FetchUnit_bus_skew_routed.pb -rpx FetchUnit_bus_skew_routed.rpx
|
||||
| Design : FetchUnit
|
||||
| Date : Wed Mar 13 11:13:49 2019
|
||||
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
|
||||
| Command : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
|
||||
| Design : CPU9bits
|
||||
| Device : 7k160ti-fbg484
|
||||
| Speed File : -2L PRODUCTION 1.12 2017-02-17
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Bus Skew Report
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Wed Feb 20 11:37:30 2019
|
||||
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
| Command : report_clock_utilization -file FetchUnit_clock_utilization_routed.rpt
|
||||
| Design : FetchUnit
|
||||
| Date : Wed Mar 13 11:13:49 2019
|
||||
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
|
||||
| Command : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt
|
||||
| Design : CPU9bits
|
||||
| Device : 7k160ti-fbg484
|
||||
| Speed File : -2L PRODUCTION 1.12 2017-02-17
|
||||
| Temperature Grade : I
|
||||
--------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------
|
||||
|
||||
Clock Utilization Report
|
||||
|
||||
@@ -19,8 +19,6 @@ Table of Contents
|
||||
3. Global Clock Source Details
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
5. Clock Regions : Global Clock Summary
|
||||
6. Device Cell Placement Summary for Global Clock g0
|
||||
7. Clock Region Cell Placement per Global Clock: Region X0Y1
|
||||
|
||||
1. Clock Primitive Utilization
|
||||
------------------------------
|
||||
@@ -28,7 +26,7 @@ Table of Contents
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| Type | Used | Available | LOC | Clock Region | Pblock |
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| BUFGCTRL | 1 | 32 | 0 | 0 | 0 |
|
||||
| BUFGCTRL | 0 | 32 | 0 | 0 | 0 |
|
||||
| BUFH | 0 | 120 | 0 | 0 | 0 |
|
||||
| BUFIO | 0 | 32 | 0 | 0 | 0 |
|
||||
| BUFMR | 0 | 16 | 0 | 0 | 0 |
|
||||
@@ -41,11 +39,9 @@ Table of Contents
|
||||
2. Global Clock Resources
|
||||
-------------------------
|
||||
|
||||
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
|
||||
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+
|
||||
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
|
||||
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
|
||||
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 9 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG |
|
||||
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
|
||||
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
|
||||
@@ -53,11 +49,9 @@ Table of Contents
|
||||
3. Global Clock Source Details
|
||||
------------------------------
|
||||
|
||||
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
|
||||
+-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+
|
||||
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
|
||||
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
|
||||
| src0 | g0 | IBUF/O | None | IOB_X0Y78 | X0Y1 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF |
|
||||
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
|
||||
+-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
|
||||
@@ -72,7 +66,7 @@ Table of Contents
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
|
||||
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
|
||||
| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 9 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
|
||||
| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
|
||||
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
|
||||
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
|
||||
| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
|
||||
@@ -94,61 +88,12 @@ All Modules
|
||||
| Y4 | 0 | 0 |
|
||||
| Y3 | 0 | 0 |
|
||||
| Y2 | 0 | 0 |
|
||||
| Y1 | 1 | 0 |
|
||||
| Y1 | 0 | 0 |
|
||||
| Y0 | 0 | 0 |
|
||||
+----+----+----+
|
||||
|
||||
|
||||
6. Device Cell Placement Summary for Global Clock g0
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
|
||||
| g0 | BUFG/O | n/a | | | | 9 | 0 | 0 | 0 | clk_IBUF_BUFG |
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
|
||||
* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+----+----+
|
||||
| | X0 | X1 |
|
||||
+----+----+----+
|
||||
| Y4 | 0 | 0 |
|
||||
| Y3 | 0 | 0 |
|
||||
| Y2 | 0 | 0 |
|
||||
| Y1 | 9 | 0 |
|
||||
| Y0 | 0 | 0 |
|
||||
+----+----+----+
|
||||
|
||||
|
||||
7. Clock Region Cell Placement per Global Clock: Region X0Y1
|
||||
------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
|
||||
| g0 | n/a | BUFG/O | None | 9 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
|
||||
# Location of BUFG Primitives
|
||||
set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst]
|
||||
|
||||
# Location of IO Primitives which is load of clock spine
|
||||
|
||||
# Location of clock ports
|
||||
set_property LOC IOB_X0Y78 [get_ports clk]
|
||||
|
||||
# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0"
|
||||
#startgroup
|
||||
create_pblock {CLKAG_clk_IBUF_BUFG}
|
||||
add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]]
|
||||
resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}
|
||||
#endgroup
|
||||
@@ -1,12 +1,12 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Wed Feb 20 11:36:57 2019
|
||||
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
| Command : report_control_sets -verbose -file FetchUnit_control_sets_placed.rpt
|
||||
| Design : FetchUnit
|
||||
| Date : Wed Mar 13 11:13:14 2019
|
||||
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
|
||||
| Command : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
|
||||
| Design : CPU9bits
|
||||
| Device : xc7k160ti
|
||||
--------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------
|
||||
|
||||
Control Set Information
|
||||
|
||||
@@ -23,8 +23,8 @@ Table of Contents
|
||||
+----------------------------------------------------------+-------+
|
||||
| Status | Count |
|
||||
+----------------------------------------------------------+-------+
|
||||
| Number of unique control sets | 1 |
|
||||
| Unused register locations in slices containing registers | 7 |
|
||||
| Number of unique control sets | 0 |
|
||||
| Unused register locations in slices containing registers | 0 |
|
||||
+----------------------------------------------------------+-------+
|
||||
|
||||
|
||||
@@ -34,8 +34,6 @@ Table of Contents
|
||||
+--------+--------------+
|
||||
| Fanout | Control Sets |
|
||||
+--------+--------------+
|
||||
| 9 | 1 |
|
||||
+--------+--------------+
|
||||
|
||||
|
||||
3. Flip-Flop Distribution
|
||||
@@ -46,7 +44,7 @@ Table of Contents
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
| No | No | No | 0 | 0 |
|
||||
| No | No | Yes | 0 | 0 |
|
||||
| No | Yes | No | 9 | 2 |
|
||||
| No | Yes | No | 0 | 0 |
|
||||
| Yes | No | No | 0 | 0 |
|
||||
| Yes | No | Yes | 0 | 0 |
|
||||
| Yes | Yes | No | 0 | 0 |
|
||||
@@ -56,10 +54,8 @@ Table of Contents
|
||||
4. Detailed Control Set Information
|
||||
-----------------------------------
|
||||
|
||||
+----------------+---------------+------------------+------------------+----------------+
|
||||
+--------------+---------------+------------------+------------------+----------------+
|
||||
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
|
||||
+----------------+---------------+------------------+------------------+----------------+
|
||||
| clk_IBUF_BUFG | | reset_IBUF | 2 | 9 |
|
||||
+----------------+---------------+------------------+------------------+----------------+
|
||||
+--------------+---------------+------------------+------------------+----------------+
|
||||
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Wed Feb 20 11:37:29 2019
|
||||
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
| Command : report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx
|
||||
| Design : FetchUnit
|
||||
| Date : Wed Mar 13 11:13:13 2019
|
||||
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
|
||||
| Command : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
|
||||
| Design : CPU9bits
|
||||
| Device : xc7k160tifbg484-2L
|
||||
| Speed File : -2L
|
||||
| Design State : Fully Routed
|
||||
---------------------------------------------------------------------------------------------------------------------
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
@@ -37,12 +37,12 @@ Table of Contents
|
||||
-----------------
|
||||
NSTD-1#1 Critical Warning
|
||||
Unspecified I/O Standard
|
||||
21 out of 21 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AddrIn[8:0], AddrOut[8:0], op_idx[0], clk, reset.
|
||||
1 out of 1 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: done.
|
||||
Related violations: <none>
|
||||
|
||||
UCIO-1#1 Critical Warning
|
||||
Unconstrained Logical Port
|
||||
21 out of 21 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AddrIn[8:0], AddrOut[8:0], op_idx[0], clk, reset.
|
||||
1 out of 1 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: done.
|
||||
Related violations: <none>
|
||||
|
||||
CFGBVS-1#1 Warning
|
||||
@@ -1,13 +1,13 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Wed Feb 20 11:36:55 2019
|
||||
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
| Command : report_drc -file FetchUnit_drc_opted.rpt -pb FetchUnit_drc_opted.pb -rpx FetchUnit_drc_opted.rpx
|
||||
| Design : FetchUnit
|
||||
| Date : Wed Mar 13 11:13:47 2019
|
||||
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
|
||||
| Command : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
|
||||
| Design : CPU9bits
|
||||
| Device : xc7k160tifbg484-2L
|
||||
| Speed File : -2L
|
||||
| Design State : Synthesized
|
||||
| Design State : Fully Routed
|
||||
------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
@@ -37,12 +37,12 @@ Table of Contents
|
||||
-----------------
|
||||
NSTD-1#1 Critical Warning
|
||||
Unspecified I/O Standard
|
||||
21 out of 21 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AddrIn[8:0], AddrOut[8:0], op_idx[0], clk, reset.
|
||||
1 out of 1 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: done.
|
||||
Related violations: <none>
|
||||
|
||||
UCIO-1#1 Critical Warning
|
||||
Unconstrained Logical Port
|
||||
21 out of 21 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AddrIn[8:0], AddrOut[8:0], op_idx[0], clk, reset.
|
||||
1 out of 1 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: done.
|
||||
Related violations: <none>
|
||||
|
||||
CFGBVS-1#1 Warning
|
||||
@@ -1,10 +1,10 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Wed Feb 20 11:36:57 2019
|
||||
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
| Command : report_io -file FetchUnit_io_placed.rpt
|
||||
| Design : FetchUnit
|
||||
| Date : Wed Mar 13 11:13:14 2019
|
||||
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
|
||||
| Command : report_io -file CPU9bits_io_placed.rpt
|
||||
| Design : CPU9bits
|
||||
| Device : xc7k160ti
|
||||
| Speed File : -2L
|
||||
| Package : fbg484
|
||||
@@ -25,7 +25,7 @@ Table of Contents
|
||||
+---------------+
|
||||
| Total User IO |
|
||||
+---------------+
|
||||
| 22 |
|
||||
| 12 |
|
||||
+---------------+
|
||||
|
||||
|
||||
@@ -70,9 +70,9 @@ Table of Contents
|
||||
| AA11 | | High Performance | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA13 | | High Performance | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA14 | AddrOut[3] | High Range | IO_L18P_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
|
||||
| AA15 | AddrOut[2] | High Range | IO_L18N_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
|
||||
| AA16 | AddrOut[5] | High Range | IO_L17P_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
|
||||
| AA14 | | High Range | IO_L18P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AA15 | | High Range | IO_L18N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AA16 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
|
||||
| AA18 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AA19 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
@@ -93,10 +93,10 @@ Table of Contents
|
||||
| AB12 | | High Performance | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB13 | | High Performance | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
|
||||
| AB15 | AddrOut[7] | High Range | IO_L16P_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
|
||||
| AB16 | AddrOut[6] | High Range | IO_L16N_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
|
||||
| AB17 | AddrOut[4] | High Range | IO_L17N_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
|
||||
| AB18 | AddrOut[8] | High Range | IO_L15N_T2_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
|
||||
| AB15 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AB16 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AB17 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AB18 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB20 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AB21 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
@@ -402,7 +402,7 @@ Table of Contents
|
||||
| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| R16 | reset | High Range | IO_L20P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
|
||||
| R16 | | High Range | IO_L20P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| R17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R18 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R19 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
@@ -423,8 +423,8 @@ Table of Contents
|
||||
| T12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| T13 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| T14 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| T15 | AddrIn[2] | High Range | IO_L24P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
|
||||
| T16 | op_idx[0] | High Range | IO_L20N_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
|
||||
| T15 | | High Range | IO_L24P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T16 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T18 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T19 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
@@ -445,8 +445,8 @@ Table of Contents
|
||||
| U12 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| U13 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U15 | AddrIn[1] | High Range | IO_L24N_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
|
||||
| U16 | AddrOut[1] | High Range | IO_L19P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
|
||||
| U15 | | High Range | IO_L24N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| U16 | | High Range | IO_L19P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| U17 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| U18 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| U19 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
|
||||
@@ -466,13 +466,13 @@ Table of Contents
|
||||
| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V12 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V13 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V14 | AddrIn[0] | High Range | IO_25_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
|
||||
| V15 | AddrIn[4] | High Range | IO_L23P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
|
||||
| V14 | done | High Range | IO_25_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
|
||||
| V15 | | High Range | IO_L23P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
|
||||
| V17 | AddrOut[0] | High Range | IO_L19N_T3_VREF_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
|
||||
| V17 | | High Range | IO_L19N_T3_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| V18 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| V19 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| V20 | clk | High Range | IO_L11P_T1_SRCC_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
|
||||
| V20 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V22 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| W1 | | High Performance | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
@@ -488,9 +488,9 @@ Table of Contents
|
||||
| W11 | | High Performance | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W12 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W13 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| W14 | AddrIn[6] | High Range | IO_L22P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
|
||||
| W15 | AddrIn[3] | High Range | IO_L23N_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
|
||||
| W16 | AddrIn[8] | High Range | IO_L21P_T3_DQS_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
|
||||
| W14 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| W15 | | High Range | IO_L23N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| W16 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| W17 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| W19 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
@@ -510,9 +510,9 @@ Table of Contents
|
||||
| Y11 | | High Performance | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y12 | | High Performance | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y13 | | High Performance | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y14 | AddrIn[5] | High Range | IO_L22N_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
|
||||
| Y14 | | High Range | IO_L22N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y16 | AddrIn[7] | High Range | IO_L21N_T3_DQS_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
|
||||
| Y16 | | High Range | IO_L21N_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| Y17 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| Y18 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| Y19 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
BIN
lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb
Normal file
BIN
lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb
Normal file
Binary file not shown.
34
lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt
Normal file
34
lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt
Normal file
@@ -0,0 +1,34 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Wed Mar 13 11:13:48 2019
|
||||
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
|
||||
| Command : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
|
||||
| Design : CPU9bits
|
||||
| Device : xc7k160tifbg484-2L
|
||||
| Speed File : -2L
|
||||
| Design State : Fully Routed
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Methodology
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: design_1
|
||||
Design limits: <entire design considered>
|
||||
Max violations: <unlimited>
|
||||
Violations found: 0
|
||||
+------+----------+-------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+------+----------+-------------+------------+
|
||||
+------+----------+-------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
|
||||
BIN
lab2CA.runs/impl_1/CPU9bits_opt.dcp
Normal file
BIN
lab2CA.runs/impl_1/CPU9bits_opt.dcp
Normal file
Binary file not shown.
BIN
lab2CA.runs/impl_1/CPU9bits_placed.dcp
Normal file
BIN
lab2CA.runs/impl_1/CPU9bits_placed.dcp
Normal file
Binary file not shown.
138
lab2CA.runs/impl_1/CPU9bits_power_routed.rpt
Normal file
138
lab2CA.runs/impl_1/CPU9bits_power_routed.rpt
Normal file
@@ -0,0 +1,138 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Wed Mar 13 11:13:48 2019
|
||||
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
|
||||
| Command : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
|
||||
| Design : CPU9bits
|
||||
| Device : xc7k160tifbg484-2L
|
||||
| Design State : routed
|
||||
| Grade : industrial
|
||||
| Process : typical
|
||||
| Characterization : Production
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Power Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
1.1 On-Chip Components
|
||||
1.2 Power Supply Summary
|
||||
1.3 Confidence Level
|
||||
2. Settings
|
||||
2.1 Environment
|
||||
2.2 Clock Constraints
|
||||
3. Detailed Reports
|
||||
3.1 By Hierarchy
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+--------------------------+--------------+
|
||||
| Total On-Chip Power (W) | 0.084 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 0.000 |
|
||||
| Device Static (W) | 0.084 |
|
||||
| Effective TJA (C/W) | 2.5 |
|
||||
| Max Ambient (C) | 99.8 |
|
||||
| Junction Temperature (C) | 25.2 |
|
||||
| Confidence Level | High |
|
||||
| Setting File | --- |
|
||||
| Simulation Activity File | --- |
|
||||
| Design Nets Matched | NA |
|
||||
+--------------------------+--------------+
|
||||
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
|
||||
|
||||
|
||||
1.1 On-Chip Components
|
||||
----------------------
|
||||
|
||||
+--------------+-----------+----------+-----------+-----------------+
|
||||
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
||||
+--------------+-----------+----------+-----------+-----------------+
|
||||
| Slice Logic | 0.000 | 1 | --- | --- |
|
||||
| Others | 0.000 | 1 | --- | --- |
|
||||
| I/O | 0.000 | 1 | 285 | 0.35 |
|
||||
| Static Power | 0.084 | | | |
|
||||
| Total | 0.084 | | | |
|
||||
+--------------+-----------+----------+-----------+-----------------+
|
||||
|
||||
|
||||
1.2 Power Supply Summary
|
||||
------------------------
|
||||
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Vccint | 0.950 | 0.023 | 0.000 | 0.023 |
|
||||
| Vccaux | 1.800 | 0.016 | 0.000 | 0.016 |
|
||||
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccbram | 0.950 | 0.001 | 0.000 | 0.001 |
|
||||
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
|
||||
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccadc | 1.800 | 0.018 | 0.000 | 0.018 |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
|
||||
|
||||
1.3 Confidence Level
|
||||
--------------------
|
||||
|
||||
+-----------------------------+------------+------------------------------------------------+--------+
|
||||
| User Input Data | Confidence | Details | Action |
|
||||
+-----------------------------+------------+------------------------------------------------+--------+
|
||||
| Design implementation state | High | Design is routed | |
|
||||
| Clock nodes activity | High | User specified more than 95% of clocks | |
|
||||
| I/O nodes activity | High | User specified more than 95% of inputs | |
|
||||
| Internal nodes activity | High | User specified more than 25% of internal nodes | |
|
||||
| Device models | High | Device models are Production | |
|
||||
| | | | |
|
||||
| Overall confidence level | High | | |
|
||||
+-----------------------------+------------+------------------------------------------------+--------+
|
||||
|
||||
|
||||
2. Settings
|
||||
-----------
|
||||
|
||||
2.1 Environment
|
||||
---------------
|
||||
|
||||
+-----------------------+--------------------------+
|
||||
| Ambient Temp (C) | 25.0 |
|
||||
| ThetaJA (C/W) | 2.5 |
|
||||
| Airflow (LFM) | 250 |
|
||||
| Heat Sink | medium (Medium Profile) |
|
||||
| ThetaSA (C/W) | 4.2 |
|
||||
| Board Selection | medium (10"x10") |
|
||||
| # of Board Layers | 12to15 (12 to 15 Layers) |
|
||||
| Board Temperature (C) | 25.0 |
|
||||
+-----------------------+--------------------------+
|
||||
|
||||
|
||||
2.2 Clock Constraints
|
||||
---------------------
|
||||
|
||||
+-------+--------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+-------+--------+-----------------+
|
||||
|
||||
|
||||
3. Detailed Reports
|
||||
-------------------
|
||||
|
||||
3.1 By Hierarchy
|
||||
----------------
|
||||
|
||||
+------+-----------+
|
||||
| Name | Power (W) |
|
||||
+------+-----------+
|
||||
|
||||
|
||||
BIN
lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb
Normal file
BIN
lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb
Normal file
Binary file not shown.
BIN
lab2CA.runs/impl_1/CPU9bits_route_status.pb
Normal file
BIN
lab2CA.runs/impl_1/CPU9bits_route_status.pb
Normal file
Binary file not shown.
11
lab2CA.runs/impl_1/CPU9bits_route_status.rpt
Normal file
11
lab2CA.runs/impl_1/CPU9bits_route_status.rpt
Normal file
@@ -0,0 +1,11 @@
|
||||
Design Route Status
|
||||
: # nets :
|
||||
------------------------------------------- : ----------- :
|
||||
# of logical nets.......................... : 2 :
|
||||
# of nets not needing routing.......... : 1 :
|
||||
# of internally routed nets........ : 1 :
|
||||
# of routable nets..................... : 1 :
|
||||
# of fully routed nets............. : 1 :
|
||||
# of nets with routing errors.......... : 0 :
|
||||
------------------------------------------- : ----------- :
|
||||
|
||||
BIN
lab2CA.runs/impl_1/CPU9bits_routed.dcp
Normal file
BIN
lab2CA.runs/impl_1/CPU9bits_routed.dcp
Normal file
Binary file not shown.
@@ -1,13 +1,13 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Wed Feb 20 11:37:30 2019
|
||||
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
| Command : report_timing_summary -max_paths 10 -file FetchUnit_timing_summary_routed.rpt -pb FetchUnit_timing_summary_routed.pb -rpx FetchUnit_timing_summary_routed.rpx -warn_on_violation
|
||||
| Design : FetchUnit
|
||||
| Date : Wed Mar 13 11:13:48 2019
|
||||
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
|
||||
| Command : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
|
||||
| Design : CPU9bits
|
||||
| Device : 7k160ti-fbg484
|
||||
| Speed File : -2L PRODUCTION 1.12 2017-02-17
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Timing Summary Report
|
||||
|
||||
@@ -52,7 +52,7 @@ Table of Contents
|
||||
|
||||
1. checking no_clock
|
||||
--------------------
|
||||
There are 9 register/latch pins with no clock driven by root clock pin: clk (HIGH)
|
||||
There are 0 register/latch pins with no clock.
|
||||
|
||||
|
||||
2. checking constant_clock
|
||||
@@ -67,21 +67,21 @@ Table of Contents
|
||||
|
||||
4. checking unconstrained_internal_endpoints
|
||||
--------------------------------------------
|
||||
There are 18 pins that are not constrained for maximum delay. (HIGH)
|
||||
There are 0 pins that are not constrained for maximum delay.
|
||||
|
||||
There are 0 pins that are not constrained for maximum delay due to constant clock.
|
||||
|
||||
|
||||
5. checking no_input_delay
|
||||
--------------------------
|
||||
There are 11 input ports with no input delay specified. (HIGH)
|
||||
There are 0 input ports with no input delay specified.
|
||||
|
||||
There are 0 input ports with no input delay but user has a false path constraint.
|
||||
|
||||
|
||||
6. checking no_output_delay
|
||||
---------------------------
|
||||
There are 9 ports with no output delay specified. (HIGH)
|
||||
There are 0 ports with no output delay specified.
|
||||
|
||||
There are 0 ports with no output delay but user has a false path constraint
|
||||
|
||||
BIN
lab2CA.runs/impl_1/CPU9bits_utilization_placed.pb
Normal file
BIN
lab2CA.runs/impl_1/CPU9bits_utilization_placed.pb
Normal file
Binary file not shown.
@@ -1,13 +1,13 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Wed Feb 20 11:36:57 2019
|
||||
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file FetchUnit_utilization_placed.rpt -pb FetchUnit_utilization_placed.pb
|
||||
| Design : FetchUnit
|
||||
| Date : Wed Mar 13 11:13:14 2019
|
||||
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
|
||||
| Design : CPU9bits
|
||||
| Device : 7k160tifbg484-2L
|
||||
| Design State : Fully Placed
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
@@ -31,11 +31,11 @@ Table of Contents
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs | 15 | 0 | 101400 | 0.01 |
|
||||
| LUT as Logic | 15 | 0 | 101400 | 0.01 |
|
||||
| Slice LUTs | 0 | 0 | 101400 | 0.00 |
|
||||
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
|
||||
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
|
||||
| Slice Registers | 9 | 0 | 202800 | <0.01 |
|
||||
| Register as Flip Flop | 9 | 0 | 202800 | <0.01 |
|
||||
| Slice Registers | 0 | 0 | 202800 | 0.00 |
|
||||
| Register as Flip Flop | 0 | 0 | 202800 | 0.00 |
|
||||
| Register as Latch | 0 | 0 | 202800 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
|
||||
@@ -57,7 +57,7 @@ Table of Contents
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 9 | Yes | Reset | - |
|
||||
| 0 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
@@ -67,20 +67,17 @@ Table of Contents
|
||||
+------------------------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------------------------------------+------+-------+-----------+-------+
|
||||
| Slice | 4 | 0 | 25350 | 0.02 |
|
||||
| SLICEL | 4 | 0 | | |
|
||||
| Slice | 0 | 0 | 25350 | 0.00 |
|
||||
| SLICEL | 0 | 0 | | |
|
||||
| SLICEM | 0 | 0 | | |
|
||||
| LUT as Logic | 15 | 0 | 101400 | 0.01 |
|
||||
| using O5 output only | 0 | | | |
|
||||
| using O6 output only | 10 | | | |
|
||||
| using O5 and O6 | 5 | | | |
|
||||
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
|
||||
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
|
||||
| LUT as Distributed RAM | 0 | 0 | | |
|
||||
| LUT as Shift Register | 0 | 0 | | |
|
||||
| Slice Registers | 9 | 0 | 202800 | <0.01 |
|
||||
| Register driven from within the Slice | 9 | | | |
|
||||
| Slice Registers | 0 | 0 | 202800 | 0.00 |
|
||||
| Register driven from within the Slice | 0 | | | |
|
||||
| Register driven from outside the Slice | 0 | | | |
|
||||
| Unique Control Sets | 1 | | 25350 | <0.01 |
|
||||
| Unique Control Sets | 0 | | 25350 | 0.00 |
|
||||
+------------------------------------------+------+-------+-----------+-------+
|
||||
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
|
||||
|
||||
@@ -114,9 +111,7 @@ Table of Contents
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 21 | 0 | 285 | 7.37 |
|
||||
| IOB Master Pads | 10 | | | |
|
||||
| IOB Slave Pads | 10 | | | |
|
||||
| Bonded IOB | 1 | 0 | 285 | 0.35 |
|
||||
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
|
||||
@@ -143,7 +138,7 @@ Table of Contents
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
@@ -177,16 +172,7 @@ Table of Contents
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| IBUF | 12 | IO |
|
||||
| OBUF | 9 | IO |
|
||||
| FDRE | 9 | Flop & Latch |
|
||||
| LUT6 | 6 | LUT |
|
||||
| LUT5 | 5 | LUT |
|
||||
| LUT4 | 5 | LUT |
|
||||
| LUT3 | 2 | LUT |
|
||||
| LUT2 | 1 | LUT |
|
||||
| LUT1 | 1 | LUT |
|
||||
| BUFG | 1 | Clock |
|
||||
| OBUF | 1 | IO |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
Binary file not shown.
@@ -1,80 +0,0 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Wed Feb 20 11:37:30 2019
|
||||
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
| Command : report_methodology -file FetchUnit_methodology_drc_routed.rpt -pb FetchUnit_methodology_drc_routed.pb -rpx FetchUnit_methodology_drc_routed.rpx
|
||||
| Design : FetchUnit
|
||||
| Device : xc7k160tifbg484-2L
|
||||
| Speed File : -2L
|
||||
| Design State : Fully Routed
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Methodology
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: design_1
|
||||
Design limits: <entire design considered>
|
||||
Max violations: <unlimited>
|
||||
Violations found: 9
|
||||
+-----------+----------+-----------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+-----------+----------+-----------------------------+------------+
|
||||
| TIMING-17 | Warning | Non-clocked sequential cell | 9 |
|
||||
+-----------+----------+-----------------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
TIMING-17#1 Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin PC/Dout_reg[0]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#2 Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin PC/Dout_reg[1]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#3 Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin PC/Dout_reg[2]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#4 Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin PC/Dout_reg[3]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#5 Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin PC/Dout_reg[4]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#6 Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin PC/Dout_reg[5]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#7 Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin PC/Dout_reg[6]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#8 Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin PC/Dout_reg[7]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#9 Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin PC/Dout_reg[8]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -1,145 +0,0 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Wed Feb 20 11:37:30 2019
|
||||
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
| Command : report_power -file FetchUnit_power_routed.rpt -pb FetchUnit_power_summary_routed.pb -rpx FetchUnit_power_routed.rpx
|
||||
| Design : FetchUnit
|
||||
| Device : xc7k160tifbg484-2L
|
||||
| Design State : routed
|
||||
| Grade : industrial
|
||||
| Process : typical
|
||||
| Characterization : Production
|
||||
-------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Power Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
1.1 On-Chip Components
|
||||
1.2 Power Supply Summary
|
||||
1.3 Confidence Level
|
||||
2. Settings
|
||||
2.1 Environment
|
||||
2.2 Clock Constraints
|
||||
3. Detailed Reports
|
||||
3.1 By Hierarchy
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+--------------------------+--------------+
|
||||
| Total On-Chip Power (W) | 6.065 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 5.957 |
|
||||
| Device Static (W) | 0.108 |
|
||||
| Effective TJA (C/W) | 2.5 |
|
||||
| Max Ambient (C) | 85.0 |
|
||||
| Junction Temperature (C) | 40.0 |
|
||||
| Confidence Level | Low |
|
||||
| Setting File | --- |
|
||||
| Simulation Activity File | --- |
|
||||
| Design Nets Matched | NA |
|
||||
+--------------------------+--------------+
|
||||
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
|
||||
|
||||
|
||||
1.1 On-Chip Components
|
||||
----------------------
|
||||
|
||||
+----------------+-----------+----------+-----------+-----------------+
|
||||
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
||||
+----------------+-----------+----------+-----------+-----------------+
|
||||
| Slice Logic | 0.130 | 31 | --- | --- |
|
||||
| LUT as Logic | 0.120 | 15 | 101400 | 0.01 |
|
||||
| BUFG | 0.005 | 1 | 32 | 3.13 |
|
||||
| Register | 0.005 | 9 | 202800 | <0.01 |
|
||||
| Others | 0.000 | 1 | --- | --- |
|
||||
| Signals | 0.183 | 33 | --- | --- |
|
||||
| I/O | 5.644 | 21 | 285 | 7.37 |
|
||||
| Static Power | 0.108 | | | |
|
||||
| Total | 6.065 | | | |
|
||||
+----------------+-----------+----------+-----------+-----------------+
|
||||
|
||||
|
||||
1.2 Power Supply Summary
|
||||
------------------------
|
||||
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Vccint | 0.950 | 0.416 | 0.373 | 0.043 |
|
||||
| Vccaux | 1.800 | 0.476 | 0.459 | 0.018 |
|
||||
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco18 | 1.800 | 2.655 | 2.654 | 0.001 |
|
||||
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccbram | 0.950 | 0.001 | 0.000 | 0.001 |
|
||||
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
|
||||
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccadc | 1.800 | 0.018 | 0.000 | 0.018 |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
|
||||
|
||||
1.3 Confidence Level
|
||||
--------------------
|
||||
|
||||
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
||||
| User Input Data | Confidence | Details | Action |
|
||||
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
||||
| Design implementation state | High | Design is routed | |
|
||||
| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
|
||||
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
|
||||
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
||||
| Device models | High | Device models are Production | |
|
||||
| | | | |
|
||||
| Overall confidence level | Low | | |
|
||||
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
2. Settings
|
||||
-----------
|
||||
|
||||
2.1 Environment
|
||||
---------------
|
||||
|
||||
+-----------------------+--------------------------+
|
||||
| Ambient Temp (C) | 25.0 |
|
||||
| ThetaJA (C/W) | 2.5 |
|
||||
| Airflow (LFM) | 250 |
|
||||
| Heat Sink | medium (Medium Profile) |
|
||||
| ThetaSA (C/W) | 4.2 |
|
||||
| Board Selection | medium (10"x10") |
|
||||
| # of Board Layers | 12to15 (12 to 15 Layers) |
|
||||
| Board Temperature (C) | 25.0 |
|
||||
+-----------------------+--------------------------+
|
||||
|
||||
|
||||
2.2 Clock Constraints
|
||||
---------------------
|
||||
|
||||
+-------+--------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+-------+--------+-----------------+
|
||||
|
||||
|
||||
3. Detailed Reports
|
||||
-------------------
|
||||
|
||||
3.1 By Hierarchy
|
||||
----------------
|
||||
|
||||
+-----------+-----------+
|
||||
| Name | Power (W) |
|
||||
+-----------+-----------+
|
||||
| FetchUnit | 5.957 |
|
||||
| PC | 0.270 |
|
||||
+-----------+-----------+
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -1,11 +0,0 @@
|
||||
Design Route Status
|
||||
: # nets :
|
||||
------------------------------------------- : ----------- :
|
||||
# of logical nets.......................... : 64 :
|
||||
# of nets not needing routing.......... : 30 :
|
||||
# of internally routed nets........ : 30 :
|
||||
# of routable nets..................... : 34 :
|
||||
# of fully routed nets............. : 34 :
|
||||
# of nets with routing errors.......... : 0 :
|
||||
------------------------------------------- : ----------- :
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -1,35 +1,83 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550680547">
|
||||
<File Type="BITSTR-BMM" Name="FetchUnit_bd.bmm"/>
|
||||
<File Type="PA-TCL" Name="FetchUnit.tcl"/>
|
||||
<File Type="OPT-DCP" Name="FetchUnit_opt.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
|
||||
<File Type="OPT-HWDEF" Name="FetchUnit.hwdef"/>
|
||||
<File Type="BG-BGN" Name="FetchUnit.bgn"/>
|
||||
<File Type="PWROPT-DCP" Name="FetchUnit_pwropt.dcp"/>
|
||||
<File Type="PLACE-DCP" Name="FetchUnit_placed.dcp"/>
|
||||
<File Type="PLACE-PRE-SIMILARITY" Name="FetchUnit_incremental_reuse_pre_placed.rpt"/>
|
||||
<File Type="POSTPLACE-PWROPT-DCP" Name="FetchUnit_postplace_pwropt.dcp"/>
|
||||
<File Type="BG-BIN" Name="FetchUnit.bin"/>
|
||||
<File Type="PHYSOPT-DCP" Name="FetchUnit_physopt.dcp"/>
|
||||
<File Type="BITSTR-MSK" Name="FetchUnit.msk"/>
|
||||
<File Type="ROUTE-ERROR-DCP" Name="FetchUnit_routed_error.dcp"/>
|
||||
<File Type="ROUTE-DCP" Name="FetchUnit_routed.dcp"/>
|
||||
<File Type="ROUTE-BLACKBOX-DCP" Name="FetchUnit_routed_bb.dcp"/>
|
||||
<File Type="BITSTR-LTX" Name="FetchUnit.ltx"/>
|
||||
<File Type="BITSTR-MMI" Name="FetchUnit.mmi"/>
|
||||
<File Type="BITSTR-SYSDEF" Name="FetchUnit.sysdef"/>
|
||||
<File Type="ROUTE-TIMING-PB" Name="FetchUnit_timing_summary_routed.pb"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-DCP" Name="FetchUnit_postroute_physopt.dcp"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="FetchUnit_postroute_physopt_bb.dcp"/>
|
||||
<File Type="BG-BIT" Name="FetchUnit.bit"/>
|
||||
<File Type="BITSTR-RBT" Name="FetchUnit.rbt"/>
|
||||
<File Type="BITSTR-NKY" Name="FetchUnit.nky"/>
|
||||
<File Type="BG-DRC" Name="FetchUnit.drc"/>
|
||||
<File Type="RDI-RDI" Name="FetchUnit.vdi"/>
|
||||
<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1552489932">
|
||||
<File Type="BITSTR-BMM" Name="CPU9bits_bd.bmm"/>
|
||||
<File Type="OPT-METHODOLOGY-DRC" Name="CPU9bits_methodology_drc_opted.rpt"/>
|
||||
<File Type="INIT-TIMING" Name="CPU9bits_timing_summary_init.rpt"/>
|
||||
<File Type="ROUTE-PWR" Name="CPU9bits_power_routed.rpt"/>
|
||||
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
|
||||
<File Type="OPT-TIMING" Name="CPU9bits_timing_summary_opted.rpt"/>
|
||||
<File Type="OPT-DCP" Name="CPU9bits_opt.dcp"/>
|
||||
<File Type="ROUTE-PWR-SUM" Name="CPU9bits_power_summary_routed.pb"/>
|
||||
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
|
||||
<File Type="OPT-DRC" Name="CPU9bits_drc_opted.rpt"/>
|
||||
<File Type="OPT-HWDEF" Name="CPU9bits.hwdef"/>
|
||||
<File Type="PWROPT-DCP" Name="CPU9bits_pwropt.dcp"/>
|
||||
<File Type="PWROPT-DRC" Name="CPU9bits_drc_pwropted.rpt"/>
|
||||
<File Type="PWROPT-TIMING" Name="CPU9bits_timing_summary_pwropted.rpt"/>
|
||||
<File Type="PLACE-DCP" Name="CPU9bits_placed.dcp"/>
|
||||
<File Type="PLACE-IO" Name="CPU9bits_io_placed.rpt"/>
|
||||
<File Type="PLACE-CLK" Name="CPU9bits_clock_utilization_placed.rpt"/>
|
||||
<File Type="PLACE-UTIL" Name="CPU9bits_utilization_placed.rpt"/>
|
||||
<File Type="PLACE-UTIL-PB" Name="CPU9bits_utilization_placed.pb"/>
|
||||
<File Type="PLACE-CTRL" Name="CPU9bits_control_sets_placed.rpt"/>
|
||||
<File Type="PLACE-SIMILARITY" Name="CPU9bits_incremental_reuse_placed.rpt"/>
|
||||
<File Type="PLACE-PRE-SIMILARITY" Name="CPU9bits_incremental_reuse_pre_placed.rpt"/>
|
||||
<File Type="BG-BGN" Name="CPU9bits.bgn"/>
|
||||
<File Type="PLACE-TIMING" Name="CPU9bits_timing_summary_placed.rpt"/>
|
||||
<File Type="POSTPLACE-PWROPT-DCP" Name="CPU9bits_postplace_pwropt.dcp"/>
|
||||
<File Type="BG-BIN" Name="CPU9bits.bin"/>
|
||||
<File Type="POSTPLACE-PWROPT-TIMING" Name="CPU9bits_timing_summary_postplace_pwropted.rpt"/>
|
||||
<File Type="PHYSOPT-DCP" Name="CPU9bits_physopt.dcp"/>
|
||||
<File Type="PHYSOPT-DRC" Name="CPU9bits_drc_physopted.rpt"/>
|
||||
<File Type="BITSTR-MSK" Name="CPU9bits.msk"/>
|
||||
<File Type="PHYSOPT-TIMING" Name="CPU9bits_timing_summary_physopted.rpt"/>
|
||||
<File Type="ROUTE-ERROR-DCP" Name="CPU9bits_routed_error.dcp"/>
|
||||
<File Type="ROUTE-DCP" Name="CPU9bits_routed.dcp"/>
|
||||
<File Type="ROUTE-BLACKBOX-DCP" Name="CPU9bits_routed_bb.dcp"/>
|
||||
<File Type="ROUTE-DRC" Name="CPU9bits_drc_routed.rpt"/>
|
||||
<File Type="ROUTE-DRC-PB" Name="CPU9bits_drc_routed.pb"/>
|
||||
<File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
|
||||
<File Type="BITSTR-LTX" Name="CPU9bits.ltx"/>
|
||||
<File Type="ROUTE-DRC-RPX" Name="CPU9bits_drc_routed.rpx"/>
|
||||
<File Type="BITSTR-MMI" Name="CPU9bits.mmi"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC" Name="CPU9bits_methodology_drc_routed.rpt"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="CPU9bits_methodology_drc_routed.rpx"/>
|
||||
<File Type="BITSTR-SYSDEF" Name="CPU9bits.sysdef"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="CPU9bits_methodology_drc_routed.pb"/>
|
||||
<File Type="ROUTE-PWR-RPX" Name="CPU9bits_power_routed.rpx"/>
|
||||
<File Type="ROUTE-STATUS" Name="CPU9bits_route_status.rpt"/>
|
||||
<File Type="ROUTE-STATUS-PB" Name="CPU9bits_route_status.pb"/>
|
||||
<File Type="ROUTE-TIMINGSUMMARY" Name="CPU9bits_timing_summary_routed.rpt"/>
|
||||
<File Type="ROUTE-TIMING-PB" Name="CPU9bits_timing_summary_routed.pb"/>
|
||||
<File Type="ROUTE-TIMING-RPX" Name="CPU9bits_timing_summary_routed.rpx"/>
|
||||
<File Type="ROUTE-SIMILARITY" Name="CPU9bits_incremental_reuse_routed.rpt"/>
|
||||
<File Type="ROUTE-CLK" Name="CPU9bits_clock_utilization_routed.rpt"/>
|
||||
<File Type="ROUTE-BUS-SKEW" Name="CPU9bits_bus_skew_routed.rpt"/>
|
||||
<File Type="ROUTE-BUS-SKEW-PB" Name="CPU9bits_bus_skew_routed.pb"/>
|
||||
<File Type="ROUTE-BUS-SKEW-RPX" Name="CPU9bits_bus_skew_routed.rpx"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-DCP" Name="CPU9bits_postroute_physopt.dcp"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="CPU9bits_postroute_physopt_bb.dcp"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="CPU9bits_timing_summary_postroute_physopted.rpt"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="CPU9bits_timing_summary_postroute_physopted.pb"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="CPU9bits_timing_summary_postroute_physopted.rpx"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="CPU9bits_bus_skew_postroute_physopted.rpt"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="CPU9bits_bus_skew_postroute_physopted.pb"/>
|
||||
<File Type="BG-BIT" Name="CPU9bits.bit"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="CPU9bits_bus_skew_postroute_physopted.rpx"/>
|
||||
<File Type="BITSTR-RBT" Name="CPU9bits.rbt"/>
|
||||
<File Type="BITSTR-NKY" Name="CPU9bits.nky"/>
|
||||
<File Type="BG-DRC" Name="CPU9bits.drc"/>
|
||||
<File Type="RDI-RDI" Name="CPU9bits.vdi"/>
|
||||
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@@ -37,6 +85,13 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ControlUnit.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/FetchUnit.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@@ -44,15 +99,21 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
|
||||
<File Path="$PSRCDIR/sources_1/new/CPU9bits.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@@ -62,7 +123,7 @@
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="FetchUnit"/>
|
||||
<Option Name="TopModule" Val="CPU9bits"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
|
||||
@@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log FetchUnit.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source FetchUnit.tcl -notrace
|
||||
vivado -log CPU9bits.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -2,11 +2,11 @@
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Wed Feb 20 11:36:21 2019
|
||||
# Process ID: 644
|
||||
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
|
||||
# Command line: vivado.exe -log FetchUnit.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source FetchUnit.tcl -notrace
|
||||
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit.vdi
|
||||
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou
|
||||
# Start of session at: Wed Mar 13 11:12:42 2019
|
||||
# Process ID: 11884
|
||||
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1
|
||||
# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
|
||||
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits.vdi
|
||||
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source FetchUnit.tcl -notrace
|
||||
source CPU9bits.tcl -notrace
|
||||
|
||||
Binary file not shown.
BIN
lab2CA.runs/synth_1/CPU9bits.dcp
Normal file
BIN
lab2CA.runs/synth_1/CPU9bits.dcp
Normal file
Binary file not shown.
@@ -17,20 +17,26 @@ proc create_report { reportName command } {
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_msg_config -id {Synth 8-256} -limit 10000
|
||||
set_msg_config -id {Synth 8-638} -limit 10000
|
||||
create_project -in_memory -part xc7k160tifbg484-2L
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project]
|
||||
set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project]
|
||||
set_property webtalk.parent_dir {C:/Users/JoseIgnacio/CA Lab/lab2CA.cache/wt} [current_project]
|
||||
set_property parent.project_path {C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo c:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project]
|
||||
set_property ip_output_repo {c:/Users/JoseIgnacio/CA Lab/lab2CA.cache/ip} [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_verilog -library xil_defaultlib {
|
||||
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v
|
||||
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v
|
||||
{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v}
|
||||
{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v}
|
||||
{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v}
|
||||
{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v}
|
||||
{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v}
|
||||
{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v}
|
||||
}
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
@@ -43,12 +49,12 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top FetchUnit -part xc7k160tifbg484-2L
|
||||
synth_design -top CPU9bits -part xc7k160tifbg484-2L
|
||||
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef FetchUnit.dcp
|
||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb"
|
||||
write_checkpoint -force -noxdef CPU9bits.dcp
|
||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb"
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
341
lab2CA.runs/synth_1/CPU9bits.vds
Normal file
341
lab2CA.runs/synth_1/CPU9bits.vds
Normal file
@@ -0,0 +1,341 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Wed Mar 13 11:12:14 2019
|
||||
# Process ID: 13200
|
||||
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
|
||||
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.vds
|
||||
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source CPU9bits.tcl -notrace
|
||||
Command: synth_design -top CPU9bits -part xc7k160tifbg484-2L
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 18016
|
||||
---------------------------------------------------------------------------------
|
||||
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 363.336 ; gain = 101.195
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'decoder' (1#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
|
||||
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:774]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'register' (2#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:774]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:404]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:409]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:404]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (4#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
|
||||
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (5#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (6#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:333]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (7#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:333]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (8#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:961]
|
||||
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
|
||||
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:684]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (9#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:684]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (10#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (11#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:961]
|
||||
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:721]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (12#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:721]
|
||||
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:640]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (13#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:640]
|
||||
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (14#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:850]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (15#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:850]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:887]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (16#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:887]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:924]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (17#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:924]
|
||||
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:317]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'less_than' (18#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:317]
|
||||
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1075]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (19#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1075]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:532]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:538]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (20#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:532]
|
||||
WARNING: [Synth 8-3848] Net result_L in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'ALU' (21#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (22#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:347]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:353]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (23#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:347]
|
||||
WARNING: [Synth 8-3848] Net dataMemOut in module/entity CPU9bits does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:8]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (24#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
|
||||
WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0]
|
||||
WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0]
|
||||
WARNING: [Synth 8-3331] design shift_left has unconnected port A[8]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.191 ; gain = 158.051
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.191 ; gain = 158.051
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k160tifbg484-2L
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.191 ; gain = 158.051
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'regOut_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:269]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'aluOut_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:17]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'FU_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:19]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'addi_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:59]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'mem_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:79]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'RegEn_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:18]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'halt_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:89]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.191 ; gain = 158.051
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 144
|
||||
+---Registers :
|
||||
9 Bit Registers := 5
|
||||
+---Muxes :
|
||||
4 Input 9 Bit Muxes := 2
|
||||
2 Input 9 Bit Muxes := 5
|
||||
4 Input 4 Bit Muxes := 1
|
||||
2 Input 3 Bit Muxes := 2
|
||||
13 Input 3 Bit Muxes := 1
|
||||
13 Input 1 Bit Muxes := 6
|
||||
2 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module decoder
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
4 Input 4 Bit Muxes := 1
|
||||
Module register
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
Module mux_4_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
4 Input 9 Bit Muxes := 1
|
||||
Module add_1bit
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module mux_2_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 1
|
||||
Module ControlUnit
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 3 Bit Muxes := 2
|
||||
13 Input 3 Bit Muxes := 1
|
||||
13 Input 1 Bit Muxes := 6
|
||||
Module bit1_mux_2_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 600 (col length:100)
|
||||
BRAMs: 650 (col length: RAMB18 100 RAMB36 50)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-3333] propagating constant 1 across sequential element (\CU/halt_reg )
|
||||
WARNING: [Synth 8-3332] Sequential element (RF/d0/regOut_reg[3]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (RF/d0/regOut_reg[2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (RF/d0/regOut_reg[1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (RF/d0/regOut_reg[0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/aluOut_reg[3]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/aluOut_reg[2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/aluOut_reg[1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/aluOut_reg[0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/FU_reg[2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/FU_reg[1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/FU_reg[0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/addi_reg) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/mem_reg) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/RegEn_reg) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (CU/halt_reg) is unused and will be removed from module CPU9bits.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-----+------+
|
||||
| |Cell |Count |
|
||||
+------+-----+------+
|
||||
|1 |OBUF | 1|
|
||||
+------+-----+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-------+------+
|
||||
|1 |top | | 1|
|
||||
+------+---------+-------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 31 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 675.293 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
61 Infos, 31 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 675.293 ; gain = 426.164
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 675.293 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Mar 13 11:12:35 2019...
|
||||
BIN
lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
Normal file
BIN
lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
Normal file
Binary file not shown.
@@ -1,13 +1,13 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
-----------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Wed Feb 20 11:36:14 2019
|
||||
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb
|
||||
| Design : FetchUnit
|
||||
| Date : Wed Mar 13 11:12:35 2019
|
||||
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
| Design : CPU9bits
|
||||
| Device : 7k160tifbg484-2L
|
||||
| Design State : Synthesized
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
-----------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
@@ -30,11 +30,11 @@ Table of Contents
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 15 | 0 | 101400 | 0.01 |
|
||||
| LUT as Logic | 15 | 0 | 101400 | 0.01 |
|
||||
| Slice LUTs* | 0 | 0 | 101400 | 0.00 |
|
||||
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
|
||||
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
|
||||
| Slice Registers | 9 | 0 | 202800 | <0.01 |
|
||||
| Register as Flip Flop | 9 | 0 | 202800 | <0.01 |
|
||||
| Slice Registers | 0 | 0 | 202800 | 0.00 |
|
||||
| Register as Flip Flop | 0 | 0 | 202800 | 0.00 |
|
||||
| Register as Latch | 0 | 0 | 202800 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
|
||||
@@ -57,7 +57,7 @@ Table of Contents
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 9 | Yes | Reset | - |
|
||||
| 0 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
@@ -90,7 +90,7 @@ Table of Contents
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 21 | 0 | 285 | 7.37 |
|
||||
| Bonded IOB | 1 | 0 | 285 | 0.35 |
|
||||
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
|
||||
@@ -117,7 +117,7 @@ Table of Contents
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
@@ -151,16 +151,7 @@ Table of Contents
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| IBUF | 12 | IO |
|
||||
| OBUF | 9 | IO |
|
||||
| FDRE | 9 | Flop & Latch |
|
||||
| LUT6 | 6 | LUT |
|
||||
| LUT5 | 5 | LUT |
|
||||
| LUT4 | 5 | LUT |
|
||||
| LUT3 | 2 | LUT |
|
||||
| LUT2 | 1 | LUT |
|
||||
| LUT1 | 1 | LUT |
|
||||
| BUFG | 1 | Clock |
|
||||
| OBUF | 1 | IO |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
Binary file not shown.
@@ -1,261 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Wed Feb 20 11:35:49 2019
|
||||
# Process ID: 8280
|
||||
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log FetchUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl
|
||||
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.vds
|
||||
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source FetchUnit.tcl -notrace
|
||||
Command: synth_design -top FetchUnit -part xc7k160tifbg484-2L
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 5464
|
||||
---------------------------------------------------------------------------------
|
||||
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 359.242 ; gain = 98.211
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'register' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
|
||||
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:53]
|
||||
WARNING: [Synth 8-350] instance 'PCAdder' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:18]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:312]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:317]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:312]
|
||||
WARNING: [Synth 8-689] width (2) of port connection 'switch' does not match port width (1) of module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:28]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
|
||||
WARNING: [Synth 8-3331] design FetchUnit has unconnected port op_idx[1]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.191 ; gain = 154.160
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.191 ; gain = 154.160
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k160tifbg484-2L
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.191 ; gain = 154.160
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
|
||||
INFO: [Synth 8-5544] ROM "Dout" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.191 ; gain = 154.160
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 18
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module register
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module add_1bit
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module mux_2_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 600 (col length:100)
|
||||
BRAMs: 650 (col length: RAMB18 100 RAMB36 50)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
WARNING: [Synth 8-3331] design FetchUnit has unconnected port op_idx[1]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-----+------+
|
||||
| |Cell |Count |
|
||||
+------+-----+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |LUT1 | 1|
|
||||
|3 |LUT2 | 1|
|
||||
|4 |LUT3 | 2|
|
||||
|5 |LUT4 | 5|
|
||||
|6 |LUT5 | 5|
|
||||
|7 |LUT6 | 6|
|
||||
|8 |FDRE | 9|
|
||||
|9 |IBUF | 12|
|
||||
|10 |OBUF | 9|
|
||||
+------+-----+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+---------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+---------+------+
|
||||
|1 |top | | 51|
|
||||
|2 | PC |register | 29|
|
||||
+------+---------+---------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 4 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 682.250 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
19 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 682.250 ; gain = 421.219
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 682.250 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Feb 20 11:36:14 2019...
|
||||
Binary file not shown.
@@ -1,11 +1,23 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550680547">
|
||||
<File Type="PA-TCL" Name="FetchUnit.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="FetchUnit.vds"/>
|
||||
<File Type="RDS-DCP" Name="FetchUnit.dcp"/>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1552489932">
|
||||
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="CPU9bits_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="CPU9bits.vds"/>
|
||||
<File Type="RDS-UTIL" Name="CPU9bits_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="CPU9bits_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="CPU9bits.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="CPU9bits_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="CPU9bits_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@@ -13,6 +25,13 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ControlUnit.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/FetchUnit.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@@ -20,15 +39,21 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
|
||||
<File Path="$PSRCDIR/sources_1/new/CPU9bits.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@@ -38,7 +63,7 @@
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="FetchUnit"/>
|
||||
<Option Name="TopModule" Val="CPU9bits"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
|
||||
@@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log FetchUnit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl
|
||||
vivado -log CPU9bits.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
|
||||
|
||||
@@ -2,11 +2,11 @@
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Wed Feb 20 11:35:49 2019
|
||||
# Process ID: 8280
|
||||
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log FetchUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl
|
||||
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.vds
|
||||
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
# Start of session at: Wed Mar 13 11:12:14 2019
|
||||
# Process ID: 13200
|
||||
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
|
||||
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.vds
|
||||
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source FetchUnit.tcl -notrace
|
||||
source CPU9bits.tcl -notrace
|
||||
|
||||
Binary file not shown.
@@ -9,13 +9,14 @@ module ALU(
|
||||
|
||||
// Wires for connecting the modules to the mux
|
||||
wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H,result_I,result_J,result_K,result_L,result_M,result_N,result_O,result_P;
|
||||
|
||||
wire cout;
|
||||
// A (0000) - Add
|
||||
add_9bit add0(
|
||||
.A(operand0),
|
||||
.B(operand1),
|
||||
.Cin(1'b0),
|
||||
.Sum(result_A));
|
||||
.Sum(result_A),
|
||||
.Cout(cout));
|
||||
// B (0001) - Subtract
|
||||
sub_9bit sub0(
|
||||
.A(operand0),
|
||||
@@ -58,7 +59,7 @@ module ALU(
|
||||
.B(operand1),
|
||||
.C(result_J));
|
||||
// K (1010) - Zero
|
||||
zero zero0(
|
||||
BEQ zero0(
|
||||
.A(operand0),
|
||||
.B(result_K));
|
||||
// L (1011)
|
||||
@@ -88,6 +89,8 @@ module ALU(
|
||||
.P(result_P),
|
||||
.out(result));
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
//testbench
|
||||
|
||||
@@ -270,7 +270,7 @@ module decoder (
|
||||
2'b01: regOut <= 4'b0010;
|
||||
2'b10: regOut <= 4'b0100;
|
||||
2'b11: regOut <= 4'b1000;
|
||||
default: regOut <= 4'bxxxx;
|
||||
default: regOut <= 4'b0000;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
@@ -344,6 +344,21 @@ module mux_2_1(
|
||||
end
|
||||
endmodule
|
||||
|
||||
module bit1_mux_2_1(
|
||||
input wire switch,
|
||||
input wire A,B,
|
||||
output reg out);
|
||||
|
||||
always @(A,B,switch) begin
|
||||
case (switch)
|
||||
1'b0 : out = A;
|
||||
1'b1 : out = B;
|
||||
default : out = 1'b1;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
//testbench
|
||||
module mux_2_1_tb();
|
||||
reg s;
|
||||
@@ -519,7 +534,7 @@ module mux_16_1(
|
||||
input wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,
|
||||
output reg [8:0] out);
|
||||
|
||||
always @(A,B,C,D,E,F,G,H,switch) begin
|
||||
always @(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,switch) begin
|
||||
case (switch)
|
||||
4'b0000 : out = A;
|
||||
4'b0001 : out = B;
|
||||
@@ -949,6 +964,7 @@ module sub_9bit(
|
||||
output wire [8:0] C);
|
||||
|
||||
wire [8:0] D;
|
||||
wire cout;
|
||||
|
||||
twos_compliment_9bit two_comp0(
|
||||
.A(B),
|
||||
@@ -958,7 +974,8 @@ module sub_9bit(
|
||||
.A(A),
|
||||
.B(D),
|
||||
.Cin(1'b0),
|
||||
.Sum(C));
|
||||
.Sum(C),
|
||||
.Cout(cout));
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1011,6 +1028,7 @@ module twos_compliment_9bit(
|
||||
output wire [8:0] B);
|
||||
|
||||
wire [8:0] C;
|
||||
wire cout;
|
||||
|
||||
not_9bit not0(
|
||||
.A(A),
|
||||
@@ -1020,7 +1038,8 @@ module twos_compliment_9bit(
|
||||
.A(C),
|
||||
.B(9'b000000000),
|
||||
.Cin(1'b1),
|
||||
.Sum(B));
|
||||
.Sum(B),
|
||||
.Cout(cout));
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1053,7 +1072,7 @@ module twos_compliment_tb();
|
||||
end
|
||||
endmodule
|
||||
|
||||
module zero(
|
||||
module BEQ(
|
||||
input wire [8:0] A,
|
||||
output wire [8:0] B);
|
||||
|
||||
|
||||
@@ -2,12 +2,13 @@
|
||||
|
||||
module CPU9bits(input wire [8:0] instr,
|
||||
input wire reset, clk,
|
||||
output reg done
|
||||
output wire done
|
||||
);
|
||||
|
||||
wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;
|
||||
wire [2:0] FU, aluOp;
|
||||
wire addiS, RegEn, loadS;
|
||||
wire [2:0] FU;
|
||||
wire [3:0] aluOp;
|
||||
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1;
|
||||
|
||||
RegFile RF(
|
||||
.clk(clk),
|
||||
@@ -24,7 +25,7 @@ module CPU9bits(input wire [8:0] instr,
|
||||
FetchUnit FetchU(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.op_idx(FU[0]),
|
||||
.op_idx(fetchBranch),
|
||||
.AddrIn(FUAddr),
|
||||
.AddrOut(PCout)
|
||||
);
|
||||
@@ -43,7 +44,8 @@ module CPU9bits(input wire [8:0] instr,
|
||||
.FU(FU),
|
||||
.addi(addiS),
|
||||
.mem(loadS),
|
||||
.load(loadMux)
|
||||
.RegEn(RegEn),
|
||||
.halt(done)
|
||||
);
|
||||
|
||||
|
||||
@@ -53,7 +55,8 @@ module CPU9bits(input wire [8:0] instr,
|
||||
.A(PCout),
|
||||
.B(JBRes),
|
||||
.Cin(9'b000000000),
|
||||
.Sum(FUJB));
|
||||
.Sum(FUJB),
|
||||
.Cout(cout0));
|
||||
|
||||
mux_2_1 mux1(
|
||||
.A(op1),
|
||||
@@ -62,18 +65,25 @@ module CPU9bits(input wire [8:0] instr,
|
||||
.switch(FU[1]));
|
||||
|
||||
mux_2_1 mux2(
|
||||
.A({4'b0000,instr[4:0]}),
|
||||
.B({6'b000000,instr[2:0]}),
|
||||
.A({4'b0000,instr[4:0]}), //Jump
|
||||
.B({6'b000000,instr[2:0]}),//Branch
|
||||
.out(JBRes),
|
||||
.switch(FU[2]));
|
||||
|
||||
bit1_mux_2_1 BranMux( // BEQ MUX
|
||||
.A(FU[0]),
|
||||
.B(op1[0]),
|
||||
.out(fetchBranch),
|
||||
.switch(FU[2])); // FU[2] only goes high when BEQ
|
||||
|
||||
///--------------------------Addi Stuff
|
||||
|
||||
add_9bit Addier(
|
||||
.A({6'b000000,instr[2:0]}),
|
||||
.B(op1),
|
||||
.Cin(9'b000000000),
|
||||
.Sum(AddiOut));
|
||||
.Sum(AddiOut),
|
||||
.Cout(cout1));
|
||||
|
||||
mux_2_1 mux3(
|
||||
.A(AluOut),
|
||||
@@ -109,6 +119,7 @@ module CPU9bits_tb();
|
||||
.done(done));
|
||||
|
||||
initial begin
|
||||
#5
|
||||
reset = 0;
|
||||
#10
|
||||
reset = 1;
|
||||
|
||||
@@ -7,69 +7,88 @@ module ControlUnit(
|
||||
output reg [2:0] FU,
|
||||
output reg addi,
|
||||
output reg mem,
|
||||
output reg load,
|
||||
output reg RegEn);
|
||||
output reg RegEn,
|
||||
output reg halt);
|
||||
|
||||
always @(instIn)begin
|
||||
always @(instIn, functBit)begin
|
||||
case(instIn)
|
||||
4'b0101:
|
||||
if(functBit == 1) begin
|
||||
aluOut <= 4'b0001; //sub
|
||||
RegEn <= 1'b0;
|
||||
FU <= 3'b001; // Disable Branching
|
||||
end
|
||||
else begin
|
||||
aluOut <= 4'b0000; //Add
|
||||
RegEn <= 1'b0;
|
||||
FU <= 3'b001; // Disable Branching
|
||||
end
|
||||
4'b1101: begin
|
||||
aluOut <= 4'b0011; //nor
|
||||
RegEn <= 1'b0;
|
||||
FU <= 3'b001; // Disable Branching
|
||||
end
|
||||
4'b1110:
|
||||
if(functBit == 1) begin
|
||||
aluOut <= 4'b0100; //and
|
||||
RegEn <= 1'b0;
|
||||
FU <= 3'b001; // Disable Branching
|
||||
end
|
||||
else begin
|
||||
aluOut <= 4'b0010; //or
|
||||
RegEn <= 1'b0;
|
||||
FU <= 3'b001; // Disable Branching
|
||||
end
|
||||
4'b1111:
|
||||
if(functBit == 1) begin
|
||||
aluOut <= 4'b0110; //srl
|
||||
RegEn <= 1'b0;
|
||||
FU <= 3'b001; // Disable Branching
|
||||
end
|
||||
else begin
|
||||
aluOut <= 4'b0101; //shift left
|
||||
RegEn <= 1'b0;
|
||||
FU <= 3'b001; // Disable Branching
|
||||
end
|
||||
4'b0111: begin
|
||||
aluOut <= 4'b1001; //Less than
|
||||
RegEn <= 1'b0;
|
||||
FU <= 3'b001; // Disable Branching
|
||||
end
|
||||
4'b0110: begin
|
||||
addi <= 1'b1; // addi
|
||||
RegEn <= 1'b0;
|
||||
FU <= 3'b001; // Disable Branching
|
||||
end
|
||||
4'b1001: begin
|
||||
4'b1001: begin //We got it wrong, first bit must always be zero whenever branching happens. Fixed
|
||||
//FU <= 3'b010; // jump
|
||||
FU <= 3'b010; // jump
|
||||
RegEn <= 1'b1;
|
||||
end
|
||||
4'b1100: begin
|
||||
FU <= 3'b011; // branch
|
||||
4'b1010: begin
|
||||
//FU <= 3'b011; // branch
|
||||
FU <= 3'b110; // branch
|
||||
RegEn <= 1'b1;
|
||||
end
|
||||
4'b1000: begin
|
||||
FU <= 3'b001; // jumpreg
|
||||
//FU <= 3'b001; // jumpreg
|
||||
FU <= 3'b000; // jumpreg
|
||||
RegEn <= 1'b1;
|
||||
end
|
||||
4'b0001: begin
|
||||
mem <= 1'b0; // load
|
||||
RegEn <= 1'b0;
|
||||
FU <= 3'b001; // Disable Branching
|
||||
end
|
||||
4'b0010: begin
|
||||
mem <= 1'b1; // store
|
||||
RegEn <= 1'b1;
|
||||
FU <= 3'b001; // Disable Branching
|
||||
end
|
||||
4'b0000: begin // regs should initialize at 0, so we shouldn't need to declare it everywhere
|
||||
halt <= 1'b1; // halt
|
||||
RegEn <= 1'b1;
|
||||
FU <= 3'b001; // Disable Branching
|
||||
end
|
||||
default: aluOut <= 4'bxxxx;
|
||||
endcase
|
||||
@@ -84,7 +103,6 @@ module ControlUnit_tb();
|
||||
wire [2:0] FetchUnit;
|
||||
wire addImmediate;
|
||||
wire memory;
|
||||
wire loadIt;
|
||||
wire RegEnable;
|
||||
|
||||
|
||||
@@ -95,7 +113,6 @@ module ControlUnit_tb();
|
||||
.FU(FetchUnit),
|
||||
.addi(addImmediate),
|
||||
.mem(memory),
|
||||
.load(loadIt),
|
||||
.RegEn(RegEnable)
|
||||
);
|
||||
|
||||
|
||||
@@ -7,6 +7,7 @@ module FetchUnit(input wire clk, reset,
|
||||
|
||||
//Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a)
|
||||
wire [8:0] progC_out, result_a, result_m;
|
||||
wire cout;
|
||||
|
||||
register PC(
|
||||
.clk(clk),
|
||||
@@ -19,7 +20,8 @@ module FetchUnit(input wire clk, reset,
|
||||
.A(progC_out),
|
||||
.B(9'b000000001),
|
||||
.Cin(9'b000000000),
|
||||
.Sum(AddrOut));
|
||||
.Sum(AddrOut),
|
||||
.Cout(cout));
|
||||
|
||||
mux_2_1 PCmux(
|
||||
.A(AddrIn),
|
||||
|
||||
@@ -41,7 +41,7 @@ module RegFile(input wire clk, reset, enable,
|
||||
register r3(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.En(decOut[4]),
|
||||
.En(decOut[3]),
|
||||
.Din(write_data),
|
||||
.Dout(r3_out));
|
||||
|
||||
|
||||
@@ -3,7 +3,7 @@
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="39" Path="C:/Users/Johannes/ece3570-lab2/lab2CA.xpr">
|
||||
<Project Version="7" Minor="39" Path="C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="0a5803efda44405bb28bbf43ba22e808"/>
|
||||
|
||||
Reference in New Issue
Block a user