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Added Pipeline

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This commit is contained in:
Johannes
2019-04-06 17:51:44 -04:00
parent f34b3d4098
commit e6cb8e536b
70 changed files with 1721 additions and 1047 deletions
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33
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -260,16 +260,23 @@ endmodule
module decoder (
input wire [1:0] index,
input wire En,
output reg [3:0] regOut);
always @ (index)
case(index)
2'b00: regOut <= 4'b1110;
2'b01: regOut <= 4'b1101;
2'b10: regOut <= 4'b1011;
2'b11: regOut <= 4'b0111;
default: regOut <= 4'b1111;
endcase
if (En == 0) begin
case(index)
2'b00: regOut <= 4'b1110;
2'b01: regOut <= 4'b1101;
2'b10: regOut <= 4'b1011;
2'b11: regOut <= 4'b0111;
default: regOut <= 4'b1111;
endcase
end
else begin
regOut <= 4'b1111;
end
endmodule
//testbench
@@ -843,12 +850,12 @@ module fDPipReg(
input wire clk,
input wire reset,
input wire En,
input wire [42:0] Din,
output reg [42:0] Dout);
input wire [50:0] Din,
output reg [50:0] Dout);
always @(posedge clk) begin
if (reset == 1'b1) begin
Dout <= 23'b0000;
Dout <= 50'b00000000000000000000000000000000000000000000000000;
end
else if (En == 1'b0) begin
Dout <= Din;
@@ -860,12 +867,12 @@ module eMPipReg(
input wire clk,
input wire reset,
input wire En,
input wire [42:0] Din,
output reg [42:0] Dout);
input wire [61:0] Din,
output reg [61:0] Dout);
always @(posedge clk) begin
if (reset == 1'b1) begin
Dout <= 23'b0000;
Dout <= 60'b0000000000000000000000000000000000000000000000000000000000000000000000;
end
else if (En == 1'b0) begin
Dout <= Din;

282
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -2,244 +2,90 @@
module CPU9bits(
input wire reset, clk,
output reg [8:0] result,
output wire [8:0] result,
output wire done
);
wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N, bankData, bankOP,jumpNeg;
wire [3:0] aluOp;
wire [2:0] FU;
wire [1:0] bankS;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link, js, dataMemEn;
instructionMemory iM(
.address(PCout),
.readData(instr)
);
dataMemory dM(
.clk(clk),
.writeEnable(dataMemEn),
.writeData(op0),
.address(op1),
.readData(dataMemOut)
);
RegFile RF(
.clk(clk),
wire [8:0] RFIn,FUAddr;
wire [1:0] instr;
wire fetchBranch, RegEn;
wire [50:0] FDOut, FDPipOut;
wire [61:0] EMOut, EMPipOut;
assign result = RFIn;
FDModule FD(
.reset(reset),
.write_index(instr[4:3]),
.op0_idx(instr[4:3]),
.op1_idx(instr[2:1]),
.write_data(RFIn),
.op0(op0),
.op1(op1)
);
RegFile Bank(
.clk(clk),
.FUIdx(fetchBranch),
.En(RegEn),
.RFIn(RFIn),
.AddrIn(FUAddr),
.RFIdx(instr),
.result(FDOut),
.done(done)
);
fDPipReg pipe1(
.clk(clk),
.reset(reset),
.En(RegEn),
.Din(FDOut),
.Dout(FDPipOut)
);
EMModule EM(
.reset(reset),
.write_index(instr[2:1]),
.op0_idx(instr[2:1]),
.op1_idx(2'b00),//Doesn't matter
.write_data(op0),
.op0(bankOP),
.op1()
);
FetchUnit FetchU(
.clk(clk),
.reset(reset),
.op_idx(fetchBranch),
.AddrIn(FUAddr),
.AddrOut(PCout)
);
ALU alu(
.opcode(aluOp),
.operand0(op0),
.operand1(op1),
.result(AluOut)
);
ControlUnit CU(
.instIn(instr[8:5]),
.functBit(instr[0]),
.aluOut(aluOp),
.FU(FU),
.addi(addiS),
.mem(loadS),
.dataMemEn(dataMemEn),
.RegEn(RegEn),
.halt(done),
.link(link),
.bank(bankS),
.js(js)
);
//-----------------------Fetch Unit Stuff
add_9bit JBAdder(
.A(PCout),
.B(JBRes),
.Cin(1'b0),
.Sum(FUJB),
.Cout(cout0)
);
mux_2_1 mux0(
.A(op0),
.B(FUJB),
.out(FUAddr),
.switch(FU[1])
);
twos_compliment_9bit two_comp0(
.A({4'b0000,instr[4:0]}),
.B(jumpNeg)
);
mux_2_1 mux1(
.A({4'b0000,instr[4:0]}),
.B(jumpNeg),
.out(SE2N),
.switch(js)
);
mux_2_1 mux2(
.A(SE2N), //Jump -- Change with signer module!
.B(SE1N),//Branch -- Change with signer module!
.out(JBRes),
.switch(FU[2])
);
sign_extend_3bit SE1(
.A(instr[2:0]),
.B(SE1N)
);
bit1_mux_2_1 BranMux( // BEQ MUX
.A(FU[0]),
.B(AluOut[0]),
.out(fetchBranch),
.switch(FU[2]) // FU[2] only goes high when BEQ
);
///--------------------------Addi Stuff
add_9bit Addier(
.A(SE3N), // Change with signer module!
.B(op0),
.Cin(1'b0),
.Sum(AddiOut),
.Cout(cout1)
);
sign_extend_3bit SE3(
.A(instr[2:0]),
.B(SE3N)
);
mux_2_1 mux3(
.A(AluOut),
.B(AddiOut),
.out(loadMux),
.switch(addiS)
);
///--------------------------Mem stuff
mux_2_1 mux4(
.A(linkData),
.B(dataMemOut), // This is DATA MEM
.out(bankData),
.switch(loadS)
);
///--------------------------Bank stuff
mux_2_1 mux5(
.A(bankData),
.B(bankOP),
.out(RFIn),
.switch(bankS[0])
);
///--------------------------Link Stuff
mux_2_1 mux6(
.A(loadMux),
.B(PCout),
.out(linkData),
.switch(link)
);
always @ (instr, dataMemOut, AluOut, AddiOut)
begin
case(instr[8:5])
4'b0001: // Load Byte
result <= dataMemOut;
4'b0101: // Add/Subtract
result <= AluOut;
4'b0110: // Add Immediate
result <= AddiOut;
4'b0111: // Set if Less Than
result <= AluOut;
4'b1101: // NOR
result <= AluOut;
4'b1110: // OR/AND
result <= AluOut;
4'b1111: // Shift Right Logical/Shift Left Logical
result <= AluOut;
default:
result <= 9'bXXXXXXXXX;
endcase
end
.PipIn(FDPipOut),
.PipOut(EMOut)
);
eMPipReg pipe2(
.clk(clk),
.reset(reset),
.En(RegEn),
.Din(EMOut),
.Dout(EMPipOut)
);
WMUdule W(
.PipIn(EMPipOut),
.RFIn(RFIn),
.FUAddr(FUAddr),
.instr(instr),
.fetchBranch(fetchBranch),
.RegEn(RegEn)
);
endmodule
module CPU9bits_tb();
reg clk, reset;
wire done;
wire [8:0] result;
initial begin
clk = 1'b0;
end
always begin
#5 clk = ~clk; // Period to be determined
end
always
#5 clk = ~clk; // Period to be determined
CPU9bits CPU9bits0(
.reset(reset),
.clk(clk),
.done(done));
.done(done),
.result(result));
initial begin
clk = 1'b0;
#5
reset = 1'b1;
#10
reset = 1'b0;
#50000
// instruction = 9'b000100000;
// reset = 1'b1;
// #10
// reset = 1'b0;
// #10
// instruction = 9'b000101000;
// #10
// instruction = 9'b010100010;
// #10
// instruction = 9'b111100000;
// #10
// instruction = 9'b111100000;
// #10
// instruction = 9'b001101000;
// #10
// instruction = 9'b010001000;
// #10
// instruction = 9'b000000000;
// #10
#5
reset = 1'b1;
#10
reset = 1'b0;
#50
$finish;
end

26
lab2CA.srcs/sources_1/new/CPU9bitsRemastered.v Normal file
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@@ -0,0 +1,26 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/06/2019 01:18:50 PM
// Design Name:
// Module Name: CPU9bitsRemastered
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CPU9bitsRemastered(
);
endmodule

120
lab2CA.srcs/sources_1/new/EMModule.v Normal file
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@@ -0,0 +1,120 @@
`timescale 1ns / 1ps
module EMModule(
input wire reset, clk,
input wire [50:0] PipIn,
output wire [61:0] PipOut
);
wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn,dataMemOut,SE1N,SE2N,SE3N,bankOP,jumpNeg;
wire [3:0] aluOp;
wire [2:0] FU;
wire [1:0] bankS;
wire addiS, RegEn, loadS, fetchBranch, cout0, cout1, link, js, dataMemEn;
assign instr = PipIn[50:42];
assign op0 = PipIn[41:33];
assign op1 = PipIn[32:24];
assign PCout = PipIn[23:15];
assign addiS = PipIn[14];
assign RegEn = PipIn[13];
assign loadS = PipIn[12];
assign link = PipIn[11];
assign js = PipIn[10];
assign dataMemEn = PipIn[9];
assign aluOp = PipIn[8:5];
assign FU = PipIn[4:2];
assign bankS = PipIn[1:0];
assign PipOut = {RegEn,PCout,bankOP,FUAddr,AluOut,dataMemOut,AddiOut,instr[4:3],bankS[0],loadS,link,addiS,fetchBranch}; // concat all signals into one
dataMemory dM(
.clk(clk),
.writeEnable(dataMemEn),
.writeData(op0),
.address(op1),
.readData(dataMemOut)
);
RegFile Bank(
.clk(clk),
.reset(reset),
.write_index(instr[2:1]),
.op0_idx(instr[2:1]),
.op1_idx(2'b00),//Doesn't matter
.write_data(op0),
.op0(bankOP),
.op1(),
.En(bankS[1])
);
ALU alu(
.opcode(aluOp),
.operand0(op0),
.operand1(op1),
.result(AluOut)
);
add_9bit JBAdder(
.A(PCout),
.B(JBRes),
.Cin(1'b0),
.Sum(FUJB),
.Cout(cout0)
);
mux_2_1 mux0(
.A(op0),
.B(FUJB),
.out(FUAddr),
.switch(FU[1])
);
twos_compliment_9bit two_comp0(
.A({4'b0000,instr[4:0]}),
.B(jumpNeg)
);
mux_2_1 mux1(
.A({4'b0000,instr[4:0]}),
.B(jumpNeg),
.out(SE2N),
.switch(js)
);
mux_2_1 mux2(
.A(SE2N), //Jump -- Change with signer module!
.B(SE1N),//Branch -- Change with signer module!
.out(JBRes),
.switch(FU[2])
);
sign_extend_3bit SE1(
.A(instr[2:0]),
.B(SE1N)
);
bit1_mux_2_1 BranMux( // BEQ MUX
.A(FU[0]),
.B(AluOut[0]),
.out(fetchBranch),
.switch(FU[2]) // FU[2] only goes high when BEQ
);
///--------------------------Addi Stuff
add_9bit Addier(
.A(SE3N), // Change with signer module!
.B(op0),
.Cin(1'b0),
.Sum(AddiOut),
.Cout(cout1)
);
sign_extend_3bit SE3(
.A(instr[2:0]),
.B(SE3N)
);
endmodule

60
lab2CA.srcs/sources_1/new/FDModule.v Normal file
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@@ -0,0 +1,60 @@
`timescale 1ns / 1ps
module FDModule(
input wire reset, clk, FUIdx, En,
input wire [8:0] RFIn, AddrIn,
input wire[1:0] RFIdx,
output wire [50:0] result,
output wire done
);
wire [8:0] instr, op1, op0, PCout;
wire [3:0] aluOp;
wire [2:0] FU;
wire [1:0] bankS;
wire addiS, RegEn, loadS, halt, link, js, dataMemEn;
assign result = {instr,op0,op1,PCout,addiS,RegEn,loadS,link,js,dataMemEn,aluOp,FU,bankS}; // concat all signals into one
instructionMemory iM(
.address(PCout),
.readData(instr)
);
FetchUnit FetchU(
.clk(clk),
.reset(reset),
.op_idx(FUIdx),
.AddrIn(AddrIn),
.AddrOut(PCout)
);
RegFile RF(
.clk(clk),
.reset(reset),
.write_index(RFIdx),
.op0_idx(instr[4:3]),
.op1_idx(instr[2:1]),
.write_data(RFIn),
.op0(op0),
.op1(op1),
.En(En)
);
ControlUnit CU(
.instIn(instr[8:5]),
.functBit(instr[0]),
.aluOut(aluOp),
.FU(FU),
.addi(addiS),
.mem(loadS),
.dataMemEn(dataMemEn),
.RegEn(RegEn),
.halt(done),
.link(link),
.bank(bankS),
.js(js)
);
endmodule

5
lab2CA.srcs/sources_1/new/RegFile.v
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@@ -1,6 +1,6 @@
`timescale 1ns / 1ps
module RegFile(input wire clk, reset,
module RegFile(input wire clk, reset,En,
input wire [1:0] write_index, op0_idx, op1_idx,
input wire [8:0] write_data,
output wire [8:0] op0, op1);
@@ -12,7 +12,8 @@ module RegFile(input wire clk, reset,
decoder d0(
.index(write_index),
.regOut(decOut)
.regOut(decOut),
.En(En)
);

58
lab2CA.srcs/sources_1/new/WMUdule.v Normal file
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@@ -0,0 +1,58 @@
`timescale 1ns / 1ps
module WMUdule(
input wire [61:0] PipIn,
output wire [8:0] RFIn,FUAddr,
output wire [1:0] instr,
output wire fetchBranch, RegEn
);
wire [8:0] PCout,AddiOut,AluOut,dataMemOut,bankOP,loadMux,linkData,bankData;
wire addiS,loadS,link,bankS;
assign RegEn = PipIn[61];
assign PCout = PipIn[60:52];
assign bankOP = PipIn[51:43];
assign FUAddr = PipIn[42:34];
assign AluOut = PipIn[33:25];
assign dataMemOut = PipIn[24:16];
assign AddiOut = PipIn[15:7];
assign instr = PipIn[6:5];
assign bankS = PipIn[4];
assign loadS = PipIn[3];
assign link = PipIn[2];
assign addiS = PipIn[1];
assign fetchBranch = PipIn[0];
mux_2_1 mux3(
.A(AluOut),
.B(AddiOut),
.out(loadMux),
.switch(addiS)
);
mux_2_1 mux4(
.A(linkData),
.B(dataMemOut), // This is DATA MEM
.out(bankData),
.switch(loadS)
);
///--------------------------Bank stuff
mux_2_1 mux5(
.A(bankData),
.B(bankOP),
.out(RFIn),
.switch(bankS)
);
///--------------------------Link Stuff
mux_2_1 mux6(
.A(loadMux),
.B(PCout),
.out(linkData),
.switch(link)
);
endmodule

26
lab2CA.srcs/sources_1/new/wModule.v Normal file
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@@ -0,0 +1,26 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/06/2019 03:23:21 PM
// Design Name:
// Module Name: wModule
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module wModule(
);
endmodule